7.3 Device Functional Modes

Table 7-1. Truth Table(1)

INPUTS

INTERNAL

Q STATES

OUTPUT

Q7

MASTER

RESET

PARALLEL

ENABLE

CLOCK

ENABLE

CLOCK

SERIAL

PARALLEL

D0 D7

Q0

Q1

L

X

X

X

X

X

L

L

L

H

X

L

L

X

X

Q00

Q10

Q0

H

L

L

↑

X

a...h

a

b

h

H

H

L

↑

H

X

H

Q0n

Q6n

H

H

L

↑

L

X

L

Q0n

Q6n

H

X

H

↑

X

X

Q00

Q10

Q70

(1)

H = High Voltage Level,

L = Low Voltage Level,

X = Don’t Care,

↑ = Transition from Low to High Level,

a...h = The level of steady-state input at inputs D0 thru D7, respectively,

Q00, Q10, Q70 = The level of Q0, Q1, or Q7, respectively, before the indicated steady-state input conditions were established

Q0n, Q6n = The level of Q0 or Q6, respectively, before the most recent ↑ transition of the clock.

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CD54HC166, CD54HCT166, CD74HC166, CD74HCT166

SCHS157D – FEBRUARY 1998 – REVISED FEBRUARY 2022

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