6.2 Recommended PCB Land Pattern

www.ti.com

EXAMPLE BOARD LAYOUT

.000 PKG

0

3X (

)

1.275

(

)

0.5

(

)

2.05

(

)

0.375

(

)

2.9

3X (

)

0.3

5X (

)

1.15

5X ( )

2

(

)

2.6

(

) TYP

3.2

(

)

0.025

(

)

2.2

(

)

0.8

(

)

0.4

(

)

0.1

(

)

0.3

(

)

2.25

16X (0.6)

16X (0.25)

14X (0.45)

19X (0.45)

(

)

1.05

(

)

2.05

(

) TYP

2.75

23X (0.25)

(R0.05) TYP

(0.05) MIN

TYP

(

0.2) VIA

TYP

(R0.05) TYP

VQFN-CLIP - 1.05 mm max height

RRB0041A

PLASTIC QUAD FLATPACK - NO LEAD

4224073/A 03/2018

NOTES: (continued)

4. This package is designed to be soldered to thermal pads on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

7

LAND PATTERN EXAMPLE

SOLDER MASK DEFINED

SCALE: 20X

PKG

METAL UNDER

SOLDER MASK

TYP

SOLDER MASK

OPENING, TYP

1

6

9

10

19

20

24

25

29

30

39

40

41

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning

and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This package is designed to be soldered to thermal pads on the board. For more information, see QFN/SON

PCB Attachment (SLUA271).

www.ti.com

CSD95410RRB

SLPS723 – SEPTEMBER 2020

Copyright © 2022 Texas Instruments Incorporated

Submit Document Feedback

5

Product Folder Links: CSD95410RRB