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−1

0

1

2

3

4

5

6

Time (2

µs/div)

VDD = 5 V

Powerup to Code 1000

IDD − Current Consumption − µA

0

500

1000

1500

2000

400 420 440 460 480 500 520 540 560 580 600 620

VDD = 2.7 V

0

1

2

3

4

5

Time (25

µs/div)

VDD = 5 V

Output Loaded with

200 pF to GND

10% to 90% FSR

0.0

0.5

1.0

1.5

2.0

2.5

3.0

Time (25

µs/div)

VDD = 2.7 V

Output Loaded with

200 pF to GND

10% to 90% FSR

−6

−2

2

6

10

14

18

0

128

256

384

512

640

768

896

1023

Channel A Output

Channel B Output

VDD = 2.7 V, TA = 25°C

Digital Input Code

Channel D Output

Channel C Output

0

4

8

12

16

20

24

0

128

256

384

512

640

768

896

1023

Channel A Output

Channel D Output

Channel B Output

Channel B Output

VDD = 5 V, TA = 25°C

Digital Input Code

DAC6574

SLAS408 – DECEMBER 2003

TYPICAL CHARACTERISTICS (continued)

At T

A = +25°C, unless otherwise noted.

HISTOGRAM

EXITING

OF CURRENT CONSUMPTION

POWER-DOWN MODE

Figure 21.

Figure 22.

LARGE SIGNAL

LARGE SIGNAL

SETTLING TIME

SETTLING TIME

Figure 23.

Figure 24.

ABSOLUTE ERROR†

ABSOLUTE ERROR†

Figure 25.

Figure 26.

†Absolute error is the deviation from ideal DAC characteristics. It includes affects of offset, gain, and integral

linearity.

9