DP83849CVSSLASHNOPB datasheet(20/100 Pages) TI2

20 / 100 page

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MDIO bus in a system must have a unique physical

address.

The DP83849C supports PHY Address strapping of Port A

to even values 0 (<0000_0>) through 30 (<1111_0>). Port

B is strapped to odd values 1 (<0000_1>) through 31

(<1111_1>). Note that Port B address is always 1 greater

than Port A address.

For further detail relating to the latch-in timing requirements

of the PHY Address pins, as well as the other hardware

configuration pins, refer to the Reset summary in

Section 6.0.

Refer to Figure 2 for an example of a PHYAD connection to

external components. In this example, the PHYAD strap-

ping results in address 00010 (02h) for Port A and address

00011 (03h) for Port B.

2.3.1 MII Isolate Mode

The DP83849C can be put into MII Isolate mode by writing

to bit 10 of the BMCR register.

When in the MII isolate mode, the DP83849C does not

respond to packet data present at TXD[3:0], TX_EN inputs

and presents a high impedance on the TX_CLK, RX_CLK,

RX_DV, RX_ER, RXD[3:0], COL, and CRS outputs. When

in Isolate mode, the DP83849C will continue to respond to

all management transactions.

While in Isolate mode, the PMD output pair will not transmit

packet data but will continue to source 100BASE-TX

scrambled idles or 10BASE-T normal link pulses.

The DP83849C can Auto-Negotiate or parallel detect to a

specific technology depending on the receive signal at the

PMD input pair. A valid link can be established for the

receiver even when the DP83849C is in Isolate mode.

Figure 2. PHYAD Strapping Example

VCC

PHYAD1 = 1

PHYAD2 = 0

PHYAD3 = 0

PHYAD4= 0

DP83849CVS/NOPB Datasheet(PDF) 20 Page - Texas Instruments