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LM3489, LM3489-Q1

SNVS443C – MAY 2006 – REVISED DECEMBER 2016

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Feature Description (continued)

Figure 21. Current Sensing by VDS

The current limit is activated when the voltage at the ADJ pin exceeds the voltage at the ISENSE pin. The ISENSE

comparator triggers the 9-µs one-shot pulse generator forcing the driver to turn the PFET off. The driver turns the

PFET back on after 9 µs. If the current has not reduced below the set threshold, the cycle will repeat

continuously.

A filter capacitor, CADJ, must be placed as shown in Figure 21. CADJ filters unwanted noise so that the ISENSE

comparator will not be accidentally triggered. A value of 100 pF to 1 nF is recommended in most applications.

Higher values can be used to create a soft-start function (see Start Up).

The current limit comparator has approximately 100 ns of blanking time. This ensures that the PFET is fully on

when the current is sensed. However, under extreme conditions such as cold temperature, some PFETs may not

fully turn on within the blanking time. In this case, the current limit threshold must be increased. If the current limit

function is used, the on time must be greater than 100 ns. Under low duty cycle operation, the maximum

operating frequency is limited by this minimum on-time.

During current limit operation, the output voltage drops significantly as does operating frequency. As the load

current is reduced, the output returns to the programmed voltage. However, there is a current limit foldback

phenomenon inherent in this current limit architecture (see Figure 22).

Figure 22. Current Limit Foldback Phenomenon