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LM3489, LM3489-Q1

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SNVS443C – MAY 2006 – REVISED DECEMBER 2016

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Feature Description (continued)

At high input voltages (> 28 V) increased undershoot at the switch node can cause an increase in the current

limit threshold. To avoid this problem, a low Vf Schottky catch diode must be used (see Catch Diode Selection

(D1)). Additionally, a resistor can be placed between the ISENSE pin and the switch node. Any value in the

range of 220 Ω to 600 Ω is recommended.

7.3.3 Start Up

The current limit circuit is active during start-up. During start-up, the PFET stays on until either the current limit or

the feedback comparator is tripped

If the current limit comparator is tripped first, then take the the foldback characteristic into account. Start-up into

full load may require a higher current limit set point or the load must be applied after start-up.

One problem with selecting a higher current limit is inrush current during start-up. Increasing the capacitance

(CADJ) in parallel with RADJ results in a soft-start characteristic. CADJ and RADJ create an RC time constant forcing

current limit to activate at a lower current. The output voltage will ramp more slowly when using this technique.

There is example start-up plot for CADJ equal to 1 nF in Typical Characteristics. Lower values for CADJ will have

little to no effect on soft-start.

7.3.4 External Sense Resistor

The VDS of a PFET tends to vary significantly over temperature. This will result an equivalent variation in current

limit. To improve current limit accuracy, an external sense resistor can be connected from VIN to the source of

the PFET, as shown in Figure 23. The current sense resistor, RCS must have value comparable with RDSON of the

PFET used, typically in the range of 50 mΩ to 200 mΩ. Equation 6 in Current Limit Operation can be used by

replacing the RDSON with RCS.

Figure 23. Current Sensing by External Resistor

7.3.5 PGATE

When switching, the PGATE pin swings from VIN (off) to some voltage below VIN (on). How far the PGATE will

swing depends on several factors including the capacitance, on-time, and input voltage.

PGATE voltage swing will increase with decreasing gate capacitance. Although PGATE voltage will typically be

around VIN-5V, with very small gate capacitances, this value can increase to a typical maximum of VIN-8.3 V.

Additionally, PGATE swing voltage will increase as on-time increases. During long on-times, such as when

operating at 100% duty cycle, the PGATE voltage will eventually fall to its maximum voltage of VIN-8.3 V (typical)

regardless of the PFET gate capacitance.

The PGATE voltage will not fall below 0.4 V (typical). Therefore, when the input voltage falls below approximately

9 V, the PGATE swing voltage range is reduced. At an input voltage of 7 V, for instance, PGATE will swing from

7 V to a minimum of 0.4 V.