HO

SR1

LO

SR2

T1

T2

T1

T2

LM5035B

www.ti.com

SNVS613C – JULY 2009 – REVISED APRIL 2013

For example, if the oscillator frequency is 200 kHz, each output will cycle at 100 kHz (TS = 10 µs). Using no

programmed delay, the maximum duty cycle at this frequency is calculated to be 50%. Using a programmed sync

rectifier delay of 100 ns, the maximum duty cycle is reduced to 49%. Because there is no fixed dead-time in the

LM5035B, it is recommended that the delay pin resistor not be less than 10K. Internal delays, which are not

ensured, are the only protection against cross conduction if the programmed delay is zero, or very small.

Figure 17. HO, LO, SR1 and SR2 Timing Diagram

Synchronous Rectifier Control Outputs (SR1 & SR2)

Synchronous rectification (SR) of the transformer secondary provides higher efficiency, especially for low output

voltage converters. The reduction of rectifier forward voltage drop (0.5V - 1.5V) to 10mV - 200mV VDS voltage for

a MOSFET significantly reduces rectification losses. In a typical application, the transformer secondary winding is

center tapped, with the output power inductor in series with the center tap. The SR MOSFETs provide the ground

path for the energized secondary winding and the inductor current. Figure 17 shows that the SR2 MOSFET is

conducting while HO enables power transfer from the primary. The SR1 MOSFET must be disabled during this

period since the secondary winding connected to the SR1 MOSFET drain is twice the voltage of the center tap.

At the conclusion of the HO pulse, the inductor current continues to flow through the SR1 MOSFET body diode.

Since the body diode causes more loss than the SR MOSFET, efficiency can be improved by minimizing the T2

period while maintaining sufficient timing margin over all conditions (component tolerances, etc.) to prevent

shoot-through current. When LO enables power transfer from the primary, the SR1 MOSFET is enabled and the

SR2 MOSFET is off.

During the time that neither HO nor LO is active, the inductor current is shared between both the SR1 and SR2

MOSFETs which effectively shorts the transformer secondary and cancels the inductance in the windings. The

SR2 MOSFET is disabled before LO delivers power to the secondary to prevent power being shunted to ground.

The SR2 MOSFET body diode continues to carry about half the inductor current until the primary power raises

the SR2 MOSFET drain voltage and reverse biases the body diode. Ideally, dead-time T1 would be set to the

minimum time that allows the SR MOSFET to turn off before the SR MOSFET body diode starts conducting.

The SR1 and SR2 outputs are powered directly by the VCC regulator. Each output is capable of sourcing and

sinking 0.5A peak. Typically, the SR1 and SR2 signals control SR MOSFET gate drivers through a pulse

transformer. The actual gate sourcing and sinking currents are provided by the secondary-side bias supply and

gate drivers.

The timing of SR1 and SR2 with respect to HO and LO is shown in Figure 17. SR1 is configured out of phase

with HO and SR2 is configured out of phase with LO. The deadtime between transitions is programmable by a

resistor connected from the DLY pin to the AGND pin. Typically, RDLY is set in the range of 10kΩ to 100kΩ. The

deadtime periods can be calculated using the following formulae:

T1 = .003 x RDLY + 4.6 ns

(4)

T2 = .0007 x RDLY + 10.01 ns

(5)

When UVLO falls below 1.25V, or during hiccup current limit, both SR1 and SR2 are held low. During normal

operation, if soft-start is held low, both SR1 and SR2 will be high.

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