LMH0318RTWR datasheet(4/59 Pages) TI2

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LMH0318

SNLS508 – SEPTEMBER 2015

www.ti.com

Pin Descriptions – SPI Mode/ Mode_SEL = 1 k

Ω to VDD

I/O

DESCRIPTION

NAME

NO.

CONTROL/INDICATOR I/O

Determines Device Configuration: SPI or SMBus

1 k

Ω to VDD:

MODE_SEL

Input, 4-Level

•

SPI mode. See Initialization Set Up

SS_N

Input, 2-Level

SPI Slave Select. . This pin has internal pull up

Input, 2.5V

SCK

SPI serial clock input

LVCMOS, 2-Level

MOSI

Input, 2-Level

SPI Master Output / Slave Input. LMH0318 SPI data receive

5,14,17,

RESERVED

No Connect

Powers down device when pulled low

1 k

Ω to VDD:

•

Power down until valid signal detected

Float(Default):

•

Reserved

ENABLE

Input, 4-Level

20 k

Ω to GND:

•

Reserved

1 k

Ω to GND:

•

Power down including signal detects and Reset Registers upon

power-up

Output,

Programmable Interrupt caused by change in LOS, violation of internal

LOS_INT_N

LVCMOS Open

eye monitor threshold, or change in lock. External 4.7-k

Ω pull-up resistor

Drain, 2-Level

is required. This pin is 3.3 V LVCMOS tolerant.

Output, 2.5 V

MISO

SPI Master Input / Slave Output. LMH0318 SPI data transmit

LVCMOS, 2-Level

Indicates CDR lock detect status

High:

Output, 2.5V

LOCK

•

CDR locked

LVCMOS, 2-Level

Low:

•

CDR not locked

HIGH SPEED DIFFERENTIAL I/O

IN0+

Input, Analog

Inverting and non-inverting differential inputs. An on-chip 100

terminating resistor connects IN0+ to IN0-. Inputs require 4.7 µF AC

IN0-

Input, Analog

coupling capacitors.

IN1+

Input, Analog

Inverting and non-inverting differential inputs. An on-chip 100

terminating resistor connects IN1+ to IN1-. Inputs require 4.7 µF AC

IN1-

Input, Analog

coupling capacitors.

Output, 75

Ω CML

OUT0+

Inverting and non-inverting 75

Ω outputs. An on-chip 75 Ω terminating

Compatible

resistor connects OUT0+ and OUT0- to VDD. Outputs require 4.7 µF AC

Output, 75

Ω CML

coupling capacitors

OUT0-

Compatible

OUT1+

Output, Analog

Inverting and non-inverting differential outputs. An on-chip 100

terminating resistor connects OUT1+ to OUT1-. Outputs require 4.7 µF AC

OUT1-

Output, Analog

coupling capacitors

POWER

VDD

7, 21

2.5 V Supply

2.5 V ± 5%

VSS

10, 24

Ground

Connect directly to ground (GND)

DAP

Ground

Exposed DAP, connect to GND using at least 5 vias (see Figure 23 )

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