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LMH0318RTWR Datasheet(PDF) 7 Page - Texas Instruments |
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LMH0318RTWR Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 59 page  LMH0318 www.ti.com SNLS508 – SEPTEMBER 2015 7.5 Electrical Characteristics Over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER PD Power dissipation Locked 75 Ω OUT0 only (800 mVpp), EOM 300 mW powered down Locked OUT1 only (600 mVpp, diff), EOM powered 195 mW down Transient power during CDR lock acquisition, 75 Ω 400 500 mW OUT0 and OUT1 powered up, EOM powered down PD_RAW Power dissipation in force EQ bypass, OUT0 RAW mode (CDR bypass) 720mVpp, OUT1 600mVpp 195 mW IN0 to OUT0 and OUT1 or IN1 to OUT0 and OUT1 IN0 to OUT0, OUT1 160 mW powered down IN1 to OUT1, OUT0 80 mW powered down 4-LEVEL INPUT and 2.5 V LVCMOS DC SPECIFICATIONS VIH High level input voltage 4-level input (MODE_SEL, 0.95*VDD V ADDR0/1, ENABLE pins) VIF Float level input voltage 4-level input (MODE_SEL, 0.67*VDD V ADDR0/1, ENABLE pins) VI20K 20K to GND input voltage 4-level input (MODE_SEL, 0.33*VDD V ADDR0/1, ENABLE pins) VIL Low level input voltage 4-level input (MODE_SEL, 0.1 V ADDR0/1, ENABLE pins) VOH High level output voltage IOH = -3 mA 2 V VOL Low level output voltage IOL = 3 mA 0.4 V IIH Input high leakage current Vinput = VDD SPI Mode: LVCMOS 15 µA (SPI_SCK, SPI_SS_N) pins SMBus Mode: LVCMOS (SMB_SDA, SMB_SCL) 15 µA pins SMBus Mode: 4-Levels 20 44 80 µA (ADDR0, ADDR1) pins 4-Levels (MODE_SEL, 20 44 80 µA ENABLE) pins IIL Input low leakage current Vinput = GND SPI Mode: LVCMOS -15 µA (SPI_MOSI, SPI_SCK) pins Vinput = GND SPI Mode: LVCMOS -37 µA (SPI_SS_N) pins SMBus Mode: LVCMOS (SMB_SDA, SMB_SCL -15 µA pins SMBus Mode: 4-Levels -160 -93 -40 µA (ADDR0, ADDR1) pins 4-Levels (MODE_SEL, -160 -93 -40 µA ENABLE) pins Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: LMH0318 |
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