Time (us)

0

1

2

3

4

5

6

7

8

9

10

-6

-4

-2

0

2

4

6

8

D004

DIN

DOUT

ROUT

Time (us)

0

1

2

3

4

5

6

7

8

9

10

-6

-4

-2

0

2

4

6

8

D003

DIN

DOUT

ROUT

13

MAX3222

www.ti.com

SLLS408H – JANUARY 2000 – REVISED OCTOBER 2016

Product Folder Links: MAX3222

Submit Documentation Feedback

Copyright © 2000–2016, Texas Instruments Incorporated

9.2.2 Detailed Design Procedure

•

All DIN, PWRDOWN and EN inputs must be connected to valid low or high logic levels.

•

Select capacitor values based on VCC level for best performance.

9.2.3 Application Curves

Figure 9. Loopback Waveforms

VCC = 3.3 V, Data Rate 250 kbit/s

Figure 10. Loopback Waveforms with 1-nF load

VCC = 3.3 V, Data Rate 250 kbit/s

10 Power Supply Recommendations

VCC should be between 3 V and 5.5 V. Charge pump capacitors should be chosen using table in Table 3.

11 Layout

11.1 Layout Guidelines

Keep the external capacitor traces short. This is more important on C1 and C2 nodes that have the fastest rise

and fall times. Make the impedance from MAX3222 ground pin and circuit board's ground plane as low as

possible for best ESD performance. Use wide metal and multiple vias on both sides of ground pin