BOARD LAYOUT GUIDELINES

e =

n

e +(i R ) +4kTR

n

S

b

S

2

2

(7)

THERMAL ANALYSIS

P =10Vx11mA+(5 [4x(100

||804 ) ] )=180mW

D

W

W

2

MaximumT =+85 C+(0.18mWx140°C/W)=110°C

J

°

OPA875

www.ti.com ............................................................................................................................................ SBOS340C – DECEMBER 2006 – REVISED AUGUST 2008

Dividing this expression by the device gain (2V/V)

gives the equivalent input-referred spot noise voltage

Achieving

optimum

performance

with

a

high

at the noninverting input as shown in Equation 7.

frequency amplifier such as the OPA875 requires

careful attention to board layout parasitics and

external component types. Recommendations that

will optimize performance include:

Evaluating these two equations for the OPA875

circuit and component values shown in Figure 30

a) Minimize parasitic capacitance to any AC

gives a total output spot noise voltage of 13.6nV/

√Hz

ground for all of the signal I/O pins. Parasitic

and a total equivalent input spot noise voltage of

capacitance on the output pin can cause instability:

6.8nV/

√Hz.

This

total

input-referred

spot

noise

on the noninverting input, it can react with the source

voltage is higher than the 6.7nV/

√Hz specification for

impedance to cause unintentional bandlimiting. To

the mux voltage noise alone. This number reflects the

reduce unwanted capacitance, a window around the

noise added to the output by the bias current noise

signal I/O pins should be opened in all of the ground

times the source resistor.

and power planes around those pins. Otherwise,

ground and power planes should be unbroken

elsewhere on the board.

Heatsinking or forced airflow may be required under

b) Minimize the distance (< 0.25") from the

extreme

operating

conditions.

Maximum

desired

power-supply

pins

to

high

frequency

0.1

µF

junction temperature will set the maximum allowed

decoupling capacitors. At the device pins, the

internal power dissipation as discussed in this

ground and power plane layout should not be in close

document. In no case should the maximum junction

proximity to the signal I/O pins. Avoid narrow power

temperature be allowed to exceed +150°C.

and ground traces to minimize inductance between

the

pins

and

the

decoupling

capacitors.

The

Operating junction temperature (TJ) is given by TA +

power-supply connections (on pins 9, 11, 13, and 15)

PD × θJA. The total internal power dissipation (PD) is

should always be decoupled with these capacitors.

the sum of quiescent power (PDQ) and additional

An optional supply decoupling capacitor across the

power dissipated in the output stage (PDL) to deliver

two power supplies (for bipolar operation) will improve

load power. Quiescent power is simply the specified

2nd-harmonic distortion performance. Larger (2.2

µF

no-load supply current times the total supply voltage

to 6.8

µF) decoupling capacitors, effective at lower

across the part. PDL depends on the required output

frequency, should also be used on the main supply

signal and load but, for a grounded resistive load, be

pins. These may be placed somewhat farther from

at a maximum when the output is fixed at a voltage

the device and may be shared among several

equal to 1/2 of either supply voltage (for equal bipolar

devices in the same area of the PCB.

supplies). Under this condition PDL = VS

2/(4 × R

L),

where RL includes feedback network loading.

c) Careful selection and placement of external

components will preserve the high-frequency

Note that it is the power in the output stage and not in

performance of the OPA875. Resistors should be a

the load that determines internal power dissipation.

very low reactance type. Surface-mount resistors

As a worst-case example, compute the maximum TJ

work best and allow a tighter overall layout. Metal-film

using an OPA875IDGK in the circuit of Figure 30

and carbon composition, axially leaded resistors can

operating

at

the

maximum

specified

ambient

also

provide

good

high-frequency

performance.

temperature of +85°C with its outputs driving a

Again, keep the leads and PCB trace length as short

grounded 100

Ω load to +2.5V:

as possible. Never use wirewound type resistors in a

high-frequency

application.

Other

network

components, such as noninverting input termination

resistors, should also be placed close to the package.

This worst-case condition does not exceed the

d) Connections to other wideband devices on the

maximum

junction

temperature.

Normally,

this

board may be made with short direct traces or

extreme case is not encountered. Careful attention to

through onboard transmission lines. For short

internal power dissipation is required.

connections, consider the trace and the input to the

next device as a lumped capacitive load. Relatively

wide traces (50mils to 100mils) should be used,

preferably with ground and power planes opened up

around them.

Copyright © 2006–2008, Texas Instruments Incorporated

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