1

FEATURES

3

2

4

6

1

B

GND

A

DBV PACKAGE

(TOP VIEW)

DCK PACKAGE

(TOP VIEW)

3

2

4

6

1

B

GND

A

3

2

4

6

1

B

GND

A

DRL PACKAGE

(TOP VIEW)

See mechanical drawings for dimensions.

DIR

DIR

DIR

5

5

5

YZP PACKAGE

(BOTTOM VIEW)

C1

B1

A1

C2

B2

A2

B

DIR

A

GND

3

2

1

4

5

6

DESCRIPTION/ORDERING INFORMATION

SN74AVC1T45

SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER

WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS

SCES530G – DECEMBER 2003 – REVISED JANUARY 2008

www.ti.com

2

• Available in the Texas Instruments NanoFree™

• Typical Max Data Rates

Package

–

500 Mbps (1.8-V to 3.3-V Translation)

• Fully Configurable Dual-Rail Design Allows

–

320 Mbps (<1.8-V to 3.3-V Translation)

Each Port to Operate Over the Full 1.2-V to

–

320 Mbps (Translate to 2.5 V or 1.8 V)

3.6-V Power-Supply Range

–

280 Mbps (Translate to 1.5 V)

• V

–

240 Mbps (Translate to 1.2 V)

GND, Both Ports Are in the High-Impedance

• Latch-Up Performance Exceeds 100 mA Per

State

JESD 78, Class II

• DIR Input Circuit Referenced to V

CCA

• ESD Protection Exceeds JESD 22

• ±12-mA Output Drive at 3.3 V

–

2000-V Human-Body Model (A114-A)

• I/Os Are 4.6-V Tolerant

–

200-V Machine Model (A115-A)

• I

–

1000-V Charged-Device Model (C101)

Operation

This single-bit noninverting bus transceiver uses two separate configurable power-supply rails. The

low-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.

ORDERING INFORMATION

ORDERABLE PART NUMBER

NanoFree™ – WCSP (DSBGA)

Reel of 3000

SN74AVC1T45YZPR

_ _ _TC_

0.23-mm Large Bump – YZP (Pb-free)

SOT (SOT-23) – DBV

Reel of 3000

SN74AVC1T45DBVR

DT1_

–40

°C to 85°C

SOT (SC-70) – DCK

Reel of 3000

SN74AVC1T45DCKR

TC_

SOT (SOT-553) – DRL

Reel of 4000

SN74AVC1T45DRLR

TC_

(1)

Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

(2)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

(3)

DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site.

YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following

character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

NanoFree is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Copyright © 2003–2008, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.