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SN74LVC1404YZP Datasheet(PDF) 13 Page - Texas Instruments |
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SN74LVC1404YZP Datasheet(HTML) 13 Page - Texas Instruments |
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13 / 32 page ![]() 13 SN74LVC1404 www.ti.com SCES469F – AUGUST 2003 – REVISED MARCH 2020 Product Folder Links: SN74LVC1404 Submit Documentation Feedback Copyright © 2003–2020, Texas Instruments Incorporated Typical Application (continued) 10.2.1 Design Requirements • The open-loop gain of the unbuffered inverter decreases as power-supply voltage decreases. This decreases the closed-loop gain of the oscillator circuit. The value of Rs can be decreased to increase the closed-loop gain, while maintaining the power dissipation of the crystal within the maximum limit. • Rs and C2 form a low-pass filter and reduce spurious oscillations. Component values can be adjusted, based on the desired cutoff frequency. • C2 can be increased over C1 to increase the phase shift and help in start-up of the oscillator. Increasing C2 may affect the duty cycle of the output voltage. • At high frequency, phase shift due to Rs becomes significant. In this case, Rs can be replaced by a capacitor to reduce the phase shift. 10.2.2 Detailed Design Procedure 1. Recommended Input Conditions – Rise time and fall time specs: See (Δt/ΔV) in the Recommended Operating Conditions table. – Specified high and low levels: See (VIH and VIL) in the Recommended Operating Conditions table. – Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC. 2. Recommended Output Conditions – Load currents should not exceed 50 mA per output and 100 mA total for the part. – Outputs should not be pulled above VCC. 10.2.2.1 Testing After the selection of proper component values, the oscillator circuit should be tested, using these components, to ensure that the oscillator circuit shows required performance over the recommended operating conditions. • Without a crystal, the oscillator circuit should not oscillate. To check this, the crystal can be replaced by its equivalent parallel-resonant resistance. • When the power-supply voltage drops, the closed-loop gain of the oscillator circuit reduces. Ensure that the circuit oscillates at the appropriate frequency at the lowest VCC and highest VCC. • Ensure that the duty cycle, start-up time, and frequency drift over time is within the system requirements. |
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