TLK1501

0.6 TO 1.5 GBPS TRANSCEIVER

SLLS428F − JUNE 2000 − REVISED JANUARY 2004

10

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

detailed description (continued)

data reception latency

The serial-to-parallel data receive latency is the time from when the first serial bit arrives at the receiver until

it is clocked out in the aligned parallel word with RXD0 received as first bit. The receive latency is fixed once

the link is established. However, due to silicon process variations and implementation variables such as supply

voltage and temperature, the exact delay varies slightly. The minimum receive latency (Rlatency) is 76 bit times;

the maximum is 107 bit times. Figure 5 illustrates the timing relationship between the serial receive terminals,

the recovered word clock (RX_CLK), and the receive data bus.

16-Bit Decoded Word

20-Bit Encoded Word [0:19]

DINTXP,

DINTXN

RXD[0−15]

RX_CLK

(Rlatency)†

† Non-Jedec symbol

Figure 5. Receiver Latency

serial-to-parallel

Serial data is received on the DINRXP and DINRXN terminals. The interpolator and clock recovery circuit locks

to the data stream if the clock to be recovered is within 200 PPM of the internally generated bit rate clock. The

recovered clock is used to retime the input data stream. The serial data is then clocked into the serial-to-parallel

shift registers. The 10-bit wide parallel data is then multiplexed and fed into two separate 8-bit/10-bit decoders

where the data is then synchronized to the incoming data steam word boundary by detection of the K28.5

synchronization pattern.

comma detect and 8-bit/10-bit decoding

The TLK1501 has two parallel 8-bit/10-bit decode circuits. Each 8-bit/10-bit decoder converts 10 bit encoded

data (half of the 20 bit received word) back into 8-bits. The comma detect circuit is designed to provide for byte

synchronization to an 8-bit/10-bit transmission code. When parallel data is clocked into a parallel to serial

converter, the byte boundary that was associated with the parallel data is now lost in the serialization of the data.

When the serial data is received and converted to parallel format again, a way is needed to recognize the byte

boundary. Usually this is accomplished through the use of a synchronization pattern. This is usually a unique

pattern of 1s and 0s that either cannot occur as part of valid data or is a pattern that repeats at defined intervals.

8-bit/10-bit encoding contains a character called the comma (b0011111 or b1100000), which is used by the

comma detect circuit on the TLK1501 to align the received serial data back to its original byte boundary. The

decoder detects the K28.5 comma, generating a synchronization signal aligning the data to their 10-bit

boundaries for decoding. It then converts the data back into 8-bit data, removing the control words. The output

from the two decoders is latched into the 16-bit register synchronized to the recovered parallel data clock

(RX_CLK) and the output is valid on the rising edge of the RX_CLK.

It is possible for a single bit error in a data pattern to be interpreted as comma on an erroneous boundary. If the

erroneous comma is taken as the new byte boundary, all subsequent data is improperly decoded until a property

aligned comma is detected. To prevent a data bit error from causing a valid data packet to be interpreted as a

comma and thus cause the erroneous word alignment by the comma detection circuit, the comma word

alignment circuit is turned off after receiving a properly aligned comma after the link is established. The link is

established after three idle patterns or one valid data pattern is properly received. The comma alignment circuit

is re-enabled when the synchronization state machine detects a loss of synchronization condition (see

synchronization and initialization).