IN

IN

EN

OUT

OUT

RESET

RESET

GND

5

6

4

28

24

23

3

+

C

OUT

10 F

m

C

1

0.1 F

50V

m

V

OUT

V

IN

250kW

TPS767D3xx

TIMING DIAGRAM

V

IN

V

OUT

V

IT+

(2)

V

IT+

(2)

V

RES

V

RES

(1)

t

t

t

Output

Undefined

Output

Undefined

200ms

Delay

200ms

Delay

V

IN-

V

IN-

Lessthan5%of

theoutputvoltage

Threshold

Voltage

RESET

Output

TPS767D3xx

SLVS209H – JULY 1999 – REVISED AUGUST 2008......................................................................................................................................................... www.ti.com

Figure 1. Typical Application Circuit (Fixed Versions) for Single Channel

(1)

VRES is the minimum input voltage for a valid RESET.

(2)

VIT —Trip voltage is typically 5% lower than the output voltage (95% VOUT).

6

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