TPS40056

SLVS612 − APRIL 2006

21

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DESIGN EXAMPLE

D Input Voltage: 10 Vdc to 14.4 Vdc

D Output voltage: 1.25 V ±1% (1.2375 ≤ VO ≤1.2625)

D Output current: 8 A (maximum, steady state), 10 A (surge, 10ms duration, 10% duty cycle maximum)

D Output ripple: 33 mVP-P at 8 A

D Output load response: 0.1 V => 10% to 90% step load change, from 1 A to 7 A

D Operating temperature: −40°C to 85°C

D fSW=170 kHz

1. Calculate maximum and minimum duty cycles

d

MIN +

V

O(min)

V

IN(max)

+ 1.2375

14.4

+ 0.086

d

MAX +

V

O(max)

V

IN(min)

+ 1.2625

10

+ 0.126

2. Select switching frequency

The switching frequency is based on the minimum duty cycle ratio and the propagation delay of the current limit

comparator. In order to maintain current limit capability, the on time of the upper MOSFET, tON, must be greater

than 400 ns (see Electrical Characteristics table). Therefore

V

O(min)

V

IN(max)

+

t

ON

T

SW

or

1

T

SW

+ f

SW +

V

O(min)

V

IN(max)

T

ON

Using 450 ns to provide margin,

f

SW +

0.086

450 ns

+ 191 kHz

Since the oscillator can vary by 10%, decrease fSW, by 10%

f

SW + 0.9

191 kHz

+ 172 kHz

and therefore choose a frequency of 170 kHz.

3. Select

∆I

In this case

∆I is chosen so that the converter enters discontinuous mode at 20% of nominal load.

DI + I

O

2

0.2

+ 8

2

0.2

+ 3.2 A

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