MT7682SN datasheet(13/49 Pages) MEDIATEK

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MT7682 Datasheet

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2.2.

Boot source

There are three options of boot source:

•

Serial flash

•

SPI slave (to load binary from host)

•

SDIO slave (to load binary from host)

The host may transmit a binary through SPI slave or SDIO slave to internal system memory (SRAM). The MCU

(Cortex-M4) can execute on SRAM after transmission is complete. The boot source in boot ROM is determined

according to the flowchart shown in Figure 2.2-1. HIF_EN and HIF_SEL can be configured at power up using by

GPIO_4 and GPIO_13, respectively.

Boot from SDIO slave

HIF_EN = 1?

HIF_SEL = 1?

Boot from SPI slave

Boot from Serial flash

Figure 2.2-1. Boot source determination flow

2.3.

Clock architecture

The clock controller (see below Figure 2.3-1) distributes the clocks coming from different oscillators to the core

and the peripherals. It also manages clock gating for low-power modes and ensures clock robustness. It features:

•

Clock prescaler. To get the best trade-off between speed and current consumption, the clock frequency

to the CPU and peripherals can be adjusted by a programmable prescaler.

•

Safe clock switching. Clock sources can be changed safely at runtime through a configuration register.

•

Clock management. To reduce the power consumption, the clock controller can stop the clock to the

core, individual peripherals or memory. The AHB and APB clock supports Dynamic Clock Management

(DCM) with a dynamic clock slow down or gating when the bus fabric is idle.

•

System clock source. Two different clock sources can be used to drive the master clock (FCPU and FBUS):

o 26 MHz/40MHz Crystal Oscillator (XO), that can supply reference clock for PLLs.

o Baseband PLL1 (BBPLL1) which reference clock is XO, with a maximum frequency at 1040MHz.

o Baseband PLL2 (BBPLL2) which reference clock is XO or divided from BBPLL1, with a fixed frequency

at 960MHz.

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