ADSP-2101/

ADSP2103

DAC084S085

TFS

DT

SCLK

DIN

SCLK

SYNC

MSB

A1

A0 OP1 OP0 D7

D6

D5

D4

D3

D2

D1

D0

X

X

X

X

DATA BITS

0 0 Write to specified register but do not update outputs.

0 1 Write to specified register and update outputs.

1 0 Write to all registers and update outputs.

1 1 Power-down outputs.

LSB

0 0 DAC A

0 1 DAC B

1 0 DAC C

1 1 DAC D

17

DAC084S085

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SNAS363F – MAY 2006 – REVISED MARCH 2016

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Programming (continued)

8.5.2 Input Shift Register

The input shift register, Figure 30, has 16 bits. The first two bits are address bits. They determine whether the

register data is for DAC A, DAC B, DAC C, or DAC D. The address bits are followed by two bits that determine

the mode of operation (writing to a DAC register without updating the outputs of all four DACs, writing to a DAC

register and updating the outputs of all four DACs, writing to the register of all four DACs and updating their

outputs, or powering down all four outputs). The final twelve bits of the shift register are the data bits. The data

format is straight binary (MSB first, LSB last), with all 0s corresponding to an output of 0 V and all 1s

corresponding to a full-scale output of VREFIN – 1 LSB. The contents of the serial input register are transferred to

the DAC register on the sixteenth falling edge of SCLK. See Figure 1.

Figure 30. Input Register Contents

Normally, the SYNC line is kept low for at least 16 falling edges of SCLK and the DAC is updated on the 16th

SCLK falling edge. However, if SYNC is brought high before the 16th falling edge, the data transfer to the shift

register is aborted and the write sequence is invalid. Under this condition, the DAC register is not updated and

there is no change in the mode of operation or in the DAC output voltages.

8.5.3 DSP and Microprocessor Interfacing

Interfacing the DAC084S085 to microprocessors and DSPs is quite simple.

8.5.3.1 ADSP-2101 and ADSP2103 Interfacing

Figure 31 shows a serial interface between the DAC084S085 and the ADSP-2101 or ADSP2103. The DSP must

be set to operate in the SPORT Transmit Alternate Framing Mode. It is programmed through the SPORT control

register and must be configured for Internal Clock Operation, Active Low Framing and 16-bit Word Length.

Transmission is started by writing a word to the Tx register after the SPORT mode has been enabled.

Figure 31. ADSP-2101 and 2103 Interface

8.5.3.2 80C51 and 80L51 Interface

Figure 32 shows a serial interface between the DAC084S085 and the 80C51 or 80L51 microcontroller. The

SYNC signal comes from a bit-programmable pin on the microcontroller. The example shown here uses port line

P3.3. This line is taken low when data is transmitted to the DAC084S085. Because the 80C51 and 80L51

transmits 8-bit bytes, only eight falling clock edges occur in the transmit cycle. To load data into the DAC, the

P3.3 line must be left low after the first eight bits are transmitted. A second write cycle is initiated to transmit the

second byte of data, after which port line P3.3 is brought high. The 80C51 and 80L51 transmit routine must

recognize that the 80C51 and 80L51 transmits data with the LSB first while the DAC084S085 requires data with

the MSB first.