SDA

SCL

S

P

START condition

STO

P condition

LM48824

SNAS479D – MARCH 2009 – REVISED MAY 2013

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APPLICATION INFORMATION

I

2C COMPATIBLE INTERFACE

The LM48824 is controlled through an I2C compatible serial interface that consists of a serial data line (SDA) and

a serial clock (SCL). The clock line is uni-directional. The data line is bi-directional (open drain). The LM48824

and the master can communicate at clock rates up to 400kHz. Figure 29 shows the I2C interface timing diagram.

Data on the SDA line must be stable during the HIGH period of SCL. The LM48824 is a transmit/receive slave-

only device, reliant upon the master to generate the SCL signal. Each transmission sequence is framed by a

START condition and a STOP condition (Figure 30). Each data word, device address and data, transmitted over

the bus is 8 bits long and is always followed by an acknowledge pulse (Figure 31). The LM48824 device address

is 1100000.

I

2C BUS FORMAT

The I2C bus format is shown in Figure 31. The START signal, the transition of SDA from HIGH to LOW while

SCL is HIGH, is generated, alerting all devices on the bus that a device address is being written to the bus.

The 7-bit device address is written to the bus, most significant bit (MSB) first, followed by the R/W bit (R/W = 0

indicates the master is writing to the LM48824, R/W = 1 indicates the master wants to read data from the

LM48824). Data is latched into the device on the rising clock edge. Each address bit must be stable while SCL is

HIGH. After the last address bit is transmitted, the master device releases SDA, during which time, an

acknowledge clock pulse is generated by the slave device. If the LM48824 receives the correct address, the

device pulls the SDA line low, generating an acknowledge bit (ACK).

Once the master device registers the ACK bit, the 8-bit register address word is sent. Each data bit should be

stable while SCL is HIGH. After the 8-bit register address is sent, the LM48824 sends another ACK bit. Following

the acknowledgment of the register address, the 8-bit register data word is sent. Each data bit should be stable

while SCL is HIGH. After the 8-bit register data is sent, the LM48824 sends another ACK bit. Following the

acknowledgement of the register data word, the master issues a STOP bit, allowing SDA to go high while SCL is

high.

Figure 29. I2C Timing Diagram

Figure 30. Start and Stop Diagram

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