AD7705 datasheet(29/44 Pages) AD

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AD7705/AD7706

Rev. C | Page 29 of 44

The FSYNC input can also be used as a software start convert

command, allowing the AD7705/AD7706 to be operated in a

conventional converter fashion. In this mode, writing to the

FSYNC bit starts conversion, and the falling edge of DRDY

indicates when conversion is complete. The disadvantage of this

scheme is that the settling time of the filter must be taken into

account for every data register update; therefore, the rate at which

the data register is updated is three times slower in this mode.

Because the FSYNC bit resets the digital filter, the full settling

time of 3 × 1/output rate must elapse before a new word is

loaded to the output register. If the DRDY signal is low when

FSYNC goes to 0, the DRDY signal is not reset to high by the

FSYNC command, because the AD7705/AD7706 recognize that

there is a word in the data register that has not been read. The

DRDY line stays low until an update of the data register takes

place, at which time it goes high for 500 × tCLKIN before returning

low again. A read from the data register resets the DRDY signal

high, and it does not return low until the settling time of the

filter has elapsed and there is a valid new word in the data register.

If the DRDY line is high when the FSYNC command is issued,

the DRDY line does not return low until the settling time of the

filter has elapsed.

RESET INPUT

The RESET input on the AD7705/AD7706 resets the logic, digital

filter, analog modulator, and on-chip registers to their default states.

DRDY is driven high, and the AD7705/AD7706 ignore all

communication to their registers while the RESET input is low.

When the RESET input returns high, the AD7705/AD7706 start

to process data, and DRDY returns low in 3 × 1/output rate,

indicating a valid new word in the data register. However, the

AD7705/AD7706 operate with their default setup conditions

after a reset, and it is generally necessary to set up all registers

and perform a calibration after a RESET command.

The AD7705/AD7706 on-chip oscillator circuit continues to

function even when the RESET input is low, and the master

clock signal continues to be available on the MCLK OUT pin.

Therefore, in applications where the system clock is provided by

the AD7705/AD7706 clock, the AD7705/AD7706 produce an

uninterrupted master clock during a RESET command.

STANDBY MODE

The STBY bit in the communication register of the AD7705/

AD7706 allows the user to place the part in a power-down

mode when it is not required to provide conversion results. The

AD7705/AD7706 retain the contents of their on-chip registers,

including the data register, while in standby mode. When released

from standby mode, the parts start to process data, and a new

word is available in the data register in 3 × 1/output rate from

when a 0 is written to the STBY bit.

The STBY bit does not affect the digital interface, nor does it

affect the status of the DRDY line. If DRDY is high when the

STBY bit is brought low, it remains high until there is a valid

new word in the data register. If DRDY is low when the STBY

bit is brought low, it remains low until the data register is updated,

at which time the DRDY line returns high for 500 × tCLKIN before

returning low again. If DRDY is low when the part enters standby

mode, indicating a valid unread word in the data register, the

data register can be read while the part is in standby. At the end

of this read operation, DRDY is reset to high.

Placing the part in standby mode reduces the total current to

9 μA typical with VDD = 5 V, and 4 μA with VDD = 3 V when the

part is operated from an external master clock, provided that this

master clock has stopped. If the external clock continues to run

in standby mode, the standby current increases to 150 μA typical

with 5 V supplies, and 75 μA typical with 3.3 V supplies. If a

crystal or ceramic resonator is used as the clock source, the total

current in standby mode is 400 μA typical with 5 V supplies, and

90 μA with 3.3 V supplies. This is because the on-chip oscillator

circuit continues to run when the part is in standby mode. This

is important in applications where the system clock is provided

by the AD7705/AD7706 clock so that the AD7705/AD7706

produce an uninterrupted master clock in standby mode.

ACCURACY

Σ-Δ ADCs, like VFCs and other integrating ADCs, do not contain

a source of nonmonotonicity and inherently offer no missing

codes performance. The AD7705/AD7706 achieve excellent

linearity by using high quality, on-chip capacitors that have a

very low capacitance/voltage coefficient. The devices also achieve

low input drift by using chopper-stabilization techniques in their

input stage. To ensure excellent performance over time and

temperature, the AD7705/AD7706 use digital calibration

techniques that minimize offset and gain error.

DRIFT CONSIDERATIONS

The AD7705/AD7706 use chopper-stabilization techniques to

minimize input offset drift. Charge injection in the analog

switches and dc-leakage currents at the sampling node are the

primary sources of offset voltage drift in the converter. The dc

input leakage current is essentially independent of the selected

gain. Gain drift within the converter primarily depends on the

temperature tracking of the internal capacitors. It is not affected

by leakage currents.

Measurement errors due to offset drift or gain drift can be

eliminated at any time by recalibrating the converter. Using the

system calibration mode also minimizes offset and gain errors in

the signal conditioning circuitry. Integral and differential linearity

errors are not significantly affected by temperature changes.

AD7705 Datasheet(PDF) 29 Page - Analog Devices

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