7.2 Functional Block Diagrams

11

10

9

6

A

B

C

INH

12

3

5

1

2

13

TG

TG

TG

TG

TG

TG

4

COMMON

OUT/IN

ax

ay

bx

by

cx

cy

8

7

V

V

SS

EE

16 V

IN/OUT

DD

15

14

BINARY TO

1 OF 2

DECODERS

WITH

INHIBIT

LOGIC

LEVEL

CONVERSION

VDD

COMMON

OUT/IN

COMMON

OUT/IN

ax OR ay

bx OR by

cx OR cy

All inputs are protected by standard CMOS protection network.

Figure 7-1. Functional Block Diagram, CD4053B-Q1

7.3 Feature Description

The CD4053B-Q1 line of multiplexers and demultiplexers can accept a wide range of digital and analog signal

levels. Digital signals range from 3V to 20V, and analog signals are accepted at levels ≤ 20V. The devices have

low ON resistance, typically 125Ω over 15VP-P signal input range for VDD – VEE = 18V. This feature allows for

very little signal loss through the switch.

The CD4053B-Q1 devices also have high OFF resistance, which keeps from the devices from wasting power

when the switch is in the OFF position, with typical channel leakage of ±100pA at VDD – VEE = 18V.

Binary address decoding on the chip makes channel selection simple. When channels are changed, a break-

before-make system eliminates channel overlap.

CD4053B-Q1

SCHS469 – MARCH 2025

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