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APPLICATION INFORMATION

Theory of Operation

Input Configuration

R

0

5 0 W

Z

0

5 0 W

1:1

AD T 1−1 W T

R

5 0W

AC S igna l

Source

ADS5440

AIN

AIN

RT

100

Ω

+

−

OPA695

5 V

R1

400

Ω

ADS5440

CIN

RIN

0.1

µF

1:1

−5 V

R2

57.5

Ω

VIN

AV = 8V/V

(18 dB)

RS

100

Ω

1000

µF

RIN

AIN

AIN

ADS5440

SLAS467A – JULY 2005 – REVISED DECEMBER 2005

The ADS5440 is a 13 bit, 210 MSPS, monolithic pipeline analog to digital converter. Its bipolar analog core

operates from a 5 V supply, while the output uses a 3.3 V supply to provide LVDS compatible outputs. The

conversion process is initiated by the rising edge of the external input clock. At that instant, the differential input

signal is captured by the input track and hold (T&H) and the input sample is sequentially converted by a series of

small resolution stages, with the outputs combined in a digital correction logic block. Both the rising and the

falling clock edges are used to propagate the sample through the pipeline every half clock cycle. This process

results in a data latency of four clock cycles, after which the output data is available as a 13 bit parallel word,

coded in offset binary format.

The analog input for the ADS5440 consists of an analog differential buffer followed by a bipolar track-and-hold.

The analog buffer isolates the source driving the input of the ADC from any internal switching. The input common

mode is set internally through a 500

Ω resistor connected from 2.4 V to each of the inputs. This results in a

differential input impedance of 1 k

Ω.

For a full-scale differential input, each of the differential lines of the input signal (pins 16 and 17) swings

symmetrically between 2.4 +0.55 V and 2.4 -0.55 V. This means that each input has a maximum signal swing of

1.1 VPP for a total differential input signal swing of 2.2 VPP. The maximum swing is determined by the internal

reference voltage generator eliminating the need for any external circuitry for this purpose.

The ADS5440 obtains optimum performance when the analog inputs are driven differentially. The circuit in

Figure 35 shows one possible configuration using an RF transformer with termination either on the primary or on

the secondary of the transformer. If voltage gain is required, a step up transformer can be used. For voltage

gains that would require an impractical transformer turn ratio, a single-ended amplifier driving the transformer is

shown in Figure 36).

Figure 35. Converting a Single-Ended Input to a Differential Signal Using RF Transformers

Figure 36. Using the OPA695 With the ADS5440

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