Sr

A1

1

0

0

1

0

A0

R

A

S

X

0

0

0

0

1

X

X

N

Sr

A1

1

0

0

1

0

A0

W

A

SD

C2 C1

C0 PD1 PD0

X

X

A

0

0

0

0

D11 D10 D9

D8

A

D7

D6...D1

D0

N

P

F/S Mode

HS Mode Master Code

HS Mode Enabled

HS Mode Enabled

ADC Power-Down Mode

ADC Sampling Mode

ADC Converting Mode

Command Byte

Write-Addressing Byte

Read-Addressing Byte

HS Mode Enabled

Return to F/S Mode

(1)

ADC Power-Down Mode

(depending on power-down selection bits)

2 x (8 Bits + ack/not-ack)

From Master to Slave

A = Acknowledge (SDA low)

N = Not acknowledge (SDA high)

S = StartCondition

P = Stop Condition

Sr = Repeated Start condition

W = 0 (write)

R = 1 (read)

From Slave to Master

NOTES: (1) To remain in HS mode, use Repeated Start instead of Stop.

(2) SCLH is SCL in HS mode.

SCLH is stretched low waiting for data conversion

(2)

ADS7828-Q1

SBAS456B – DECEMBER 2008 – REVISED JANUARY 2016

www.ti.com

Figure 19. Typical Read Sequence in HS Mode

7.4.7 Reading With Reference On or Off

The internal reference defaults to off when the ADS7828 power is on. To turn the internal reference on or off, see

Table 2. If the reference (internal or external) is constantly turned on and off, a proper amount of settling time

must be added before a normal conversion cycle can be started. The exact amount of settling time needed

varies depending on the configuration.

See Figure 20 for an example of the proper internal reference turn-on sequence before issuing the typical read

sequences required for the F/S mode when an internal reference is used.

20

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