ADS7813P datasheet(17/27 Pages) TI2

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ADS7813

SBAS043C

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Figure 16 shows a QSPI-equipped microcontroller interfac-

ing to three ADS7813s. There are many possible variations

to this interface scheme. As shown, the QSPI port produces

a common CONV signal which initiates a conversion on all

three converters. After the conversions are finished, each

result is transferred in turn. The QSPI port is completely

programmable to handle the timing and transfers without

processor intervention. If the CONV signal is generated in

this way, it should be possible to make both AC and DC

measurements with the ADS7813, as the CONV signal will

have low jitter. Note that if the CONV signal is generated via

software commands, it will have a good deal of jitter and

only low frequency (DC) measurements can be made.

SPI INTERFACING

The serial peripheral interface (SPI) is directly related to the

QSPI and both Figures 15 and 16 can be used as a guide for

connecting the ADS7813 to SPI-equipped microcontrollers.

For most microcontrollers, the SPI port is capable of 8-bit

transfers only. In the case of Figure 15, be aware that the

microcontroller may have to be capable of fetching the 8

most significant bits before they are overwritten by the 8

least significant bits.

DSP56002 INTERFACING

The DSP56002 serial interface has an SPI compatibility

mode with some enhancements. Figure 17 shows an inter-

face between the ADS7813 and the DSP56002. As with the

QSPI interface of Figure 15, the DSP56002 must be pro-

grammed to enable the serial interface when a LOW to

HIGH transition on SCI occurs.

The DSP56002 can also provide the CONV signal, as shown

in Figure 18. The receive and transmit sections of the

interface are decoupled (asynchronous mode) and the trans-

mit section is set to generate a word length frame sync every

other transmit frame (frame rate divider set to 2). The

prescale modulus should be set to produce a transmit frame

at twice the desired conversion rate.

FIGURE 18. DSP56002 Interface to the ADS7813. Processor Initiates Conversions.

CONV

BUSY

DATACLK

DATA

EXT/INT

ADS7813

DSP56002

SC2

SC0

SRD

SYN = 0 (Asychronous)

GCK = 1 (Gated clock)

SCD2 = 1 (SC2 is an output)

SHFD = 0 (Shift MSB first)

WL1 = 1

WL0 = 0 (Word length = 16 bits)

FIGURE 16. QSPI Interface to Three ADS7813s.

FIGURE 17. DSP56002 Interface to the ADS7813.

CONV

BUSY

DATA

DATACLK

EXT/INT

ADS7813

SC1

SRD

SCO

DSP56002

SYN = 0 (Asychronous)

GCK = 1 (Gated clock)

SCD1 = 0 (SC1 is an input)

SHFD = 0 (Shift MSB first)

WL1 = 1 WL0 = 0 (Word length = 16 bits)

Convert Pulse

CONV

DATACLK

DATA

EXT/INT

ADS7813

PCS0

PCS1

PCS2

PCS3

SCK

MISO

QSPI

CONV

DATACLK

DATA

EXT/INT

ADS7813

CONV

DATACLK

DATA

EXT/INT

ADS7813

+5V

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