ADS7813P datasheet(14/27 Pages) TI2

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ADS7813

SBAS043C

www.ti.com

The range for the external reference is 2.3V to 2.7V. The

voltage on REF determines the full-scale range of the con-

verter and the corresponding LSB size. Increasing the refer-

ence voltage will increase the LSB size in relation to the

internal noise sources which, in turn, can improve signal-to-

noise ratio. Likewise, decreasing the reference voltage will

reduce the LSB size and signal-to-noise ratio.

CAP

The CAP pin is used to compensate the internal reference

buffer. A 1

µF tantalum capacitor in parallel with a 0.01µF

ceramic capacitor should be connected between this pin and

ground, with the ceramic capacitor placed as close to the

ADS7813 as possible. The total value of the capacitance on

the CAP pin is critical to optimum performance of the

ADS7813. A value larger than 2.0

µF could overcompensate

the buffer while a value lower than 0.5

µF may not provide

adequate compensation. The ESR (equivalent series resis-

tance) of these compensation capacitors is also critical. Keep

the total ESR under 3

Ω. See the Typical Characteristic curve,

|Worst-Case INL| vs ESR of Reference Buffer Compensation

Capacitor, for how the worst-case INL is affected by ESR.

BUF

The voltage on the BUF pin is the output of the internal

reference buffer. This pin is used to provide +2.5V to the

analog input or inputs for the various input configurations.

The BUF output can provide up to 1mA of current to an

external load. The load should be constant as a variable load

could affect the conversion result by modulating the BUF

voltage. Also note that the BUF output will show significant

glitches as each bit decision is made during a conversion.

Between conversions, the BUF output is quiet.

POWER DOWN

The ADS7813 has a power-down mode that is activated by

taking CONV LOW and then PWRD HIGH. This will

power down all of the analog circuitry including the refer-

ence, reducing power dissipation to under 50

µW. To exit the

power-down mode, CONV is taken HIGH and then PWRD

is taken LOW. Note that a conversion will be initiated if

PWRD is taken HIGH while CONV is LOW.

While in the power-down mode, the voltage on the capaci-

tors connected to CAP and REF will begin to leak off. The

voltage on the CAP capacitor leaks off much more rapidly

than on the REF capacitor (the REF input of the ADS7813

becomes high-impedance when PWRD is HIGH—this is not

true for the CAP input). When the power-down mode is

exited, these capacitors must be allowed to recharge and

settle to a 16-bit level. Figure 11 shows the amount of time

typically required to obtain a valid 16-bit result based on the

amount of time spent in power down (at room temperature).

This figure assumes that the total capacitance on the CAP

pin is 1.01

µF.

Figure 12 provides a circuit which can significantly reduce

the power up time if the power down time will be fairly brief

(a few seconds or less). A low on-resistance MOSFET is

used to disconnect the capacitance on the CAP pin from the

leakage paths internal to the ADS7813. This allows the

capacitors to retain their charge for a much longer period of

time, reducing the time required to recharge them at power

up. With this circuit, the power-down time can be extended

to tens or hundreds of milliseconds with almost instanta-

neous power up.

FIGURE 12. Improved Power-Up Response Circuit.

FIGURE 11. Power-Down to Power-Up Response.

POWER-DOWN TO POWER-UP RESPONSE

Power-Down Duration (ms)

300

250

200

150

100

0.1

100

A = +25°C

PWRD

BUSY

CONV

EXT/INT

DATA

DATACLK

GND

BUF

CAP

REF

GND

0.01µF

1µF

1RF7604

Power-Down Signal

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