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AMC1336 Datasheet(PDF) 9 Page - Texas Instruments |
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AMC1336 Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 40 page ![]() CLKIN DOUT Bitstream not valid (analog settling) DVDD ... Valid bitstream AVDD tASTART CLKIN DOUT t CLKIN t HIGH t LOW t D t H t r / tf 9 AMC1336-Q1 www.ti.com SBASA51 – MAY 2020 Product Folder Links: AMC1336-Q1 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated 6.10 Switching Characteristics over operating ambient temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fCLKIN CLKIN clock frequency 3.0 V ≤ AVDD ≤ 5.5 V 9 20 21 MHz 4.5 V ≤ AVDD ≤ 5.5 V 5 20 21 CLKIN duty cycle 40% 50% 60% tH1 DOUT hold time after rising edge of CLKIN CLOAD = 15 pF 3.5 ns tD1 Rising edge of CLKIN to DOUT valid delay CLOAD = 15 pF 15 ns tr DOUT rise time 10% to 90%, 2.7 V ≤ DVDD ≤ 3.6 V, CLOAD = 15 pF 2.5 6 ns 10% to 90%, 4.5 V ≤ DVDD ≤ 5.5 V, CLOAD = 15 pF 3.2 6 tf DOUT fall time 10% to 90%, 2.7 V ≤ DVDD ≤ 3.6 V, CLOAD = 15 pF 2.2 6 ns 10% to 90%, 4.5 V ≤ DVDD ≤ 5.5 V, CLOAD = 15 pF 2.9 6 tASTART Analog start-up time AVDD step to 3.0 V; 0.1%-settling, clock applied 0.25 ms Figure 1. Digital Interface Timing Figure 2. Device Start-Up Timing |
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