Not Recommended for New Designs

CDC906

SCAS828B – SEPTEMBER 2006 – REVISED FEBRUARY 2008...................................................................................................................................... www.ti.com

DEVICE CHARACTERISTICS

over recommended operating free-air temperature range and test load (unless otherwise noted), see Figure 1

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

(1)

OVERALL PARAMETER

All PLLs on, all outputs on,

ICC

Supply current (2)

fOUT = 80 MHz, fCLK_IN = 27 MHz,

90

115

mA

f(VCO) = 160 MHz

Power down current. Every circuit powered

ICCPD

fIN = 0 MHz, VCC = 3.6 V

50

μA

down except SMBus

Supply voltage VCC threshold for power up

VPUC

2.1

V

control circuit

All PLLs

80

200

Normal

VCO frequency of internal PLL (any of three

speed-mode(3)

f(VCO)

PLL2 with SSC

80

167

MHz

PLLs)

High-speed mode(3)

180

300

VCC = 2.5 V

250

LVCMOS output frequency range(4), See

fOUT

MHz

Figure 4

VCC = 3.3 V

300

LVCMOS PARAMETER

VIK

LVCMOS input voltage

VCC = 3 V, II = –18 mA

–1.2

V

II

LVCMOS input current (CLK_IN0 / CLK_IN1)

VI = 0 V or VCC, VCC = 3.6 V

±5

μA

IIH

LVCMOS input current (For S1/S0)

VI = VCC, VCC = 3.6 V

5

μA

IIL

LVCMOS input current (For S1/S0)

VI = 0 V, VCC = 3.6 V

-35

–10

μA

CI

Input capacitance at CLK_IN0 and CLK_IN1

VI = 0 V or VCC

3

pF

LVCMOS PARAMETER FOR VCCOUT = 3.3-V Mode

VCCOUT = 3 V, IOH = –0.1 mA

2.9

VOH

LVCMOS high-level output voltage

VCCOUT = 3 V, IOH = –4 mA

2.4

V

VCCOUT = 3 V, IOH = –6 mA

2.1

VCCOUT = 3 V, IOL = 0.1 mA

0.1

VOL

LVCMOS low-level output voltage

VCCOUT = 3 V, IOL = 4 mA

0.5

V

VCCOUT = 3 V, IOL = 6 mA

0.85

All PLL bypass

9

tPLH,

Propagation delay

ns

tPHL

VCO bypass

11

tr0/tf0

Rise and fall time for output slew rate 0

VCCOUT = 3.3 V (20%–80%)

1.7

3.3

4.8

ns

tr1/tf1

Rise and fall time for output slew rate 1

VCCOUT = 3.3 V (20%–80%)

1.5

2.5

3.2

ns

tr2/tf2

Rise and fall time for output slew rate 2

VCCOUT = 3.3 V (20%–80%)

1.2

1.6

2.1

ns

Rise and fall time for output slew rate 3

tr3/tf3

VCCOUT = 3.3 V (20%–80%)

0.4

0.6

1

ns

(Default Configuration)

1 PLL, 1 Output

fOUT = 24.576 MHz

65

95

tjit(cc)

Cycle-to-cycle jitter (5) (6)

ps

3 PLLs, 3 Outputs

fOUT = 24.576 MHz

85

135

1 PLL, 1 Output

fOUT = 24.576 MHz

90

115

tjit(per)

Peak-to-peak period jitter(5) (6)

ps

3 PLLs, 3 Outputs

fOUT = 24.576 MHz

100

150

Output skew (see (7) and Table 5)

1.6-ns rise/fall time at f(VCO) = 150 MHz,

tsk(o)

200

ps

Pdiv = 3

(1)

All typical values are at respective nominal VCC.

(2)

For calculating total supply current, add the current from Figure 2 , Figure 3 , and Figure 4 . Using high-speed mode of the VCO reduces

the current consumption significantly. See Figure 3

(3)

Normal-speed mode or high-speed mode must be selected by the VCO frequency selection bit in Byte 6, Bit [7:5]. The min f(VCO) can be

lower but impacts jitter-performance.

(4)

The maximum output frequency may be exceeded, but specifications under the Recommended Operating Condition may change and

are no longer assured. Do not exceed the maximum power dissipation of the 20-pin TSSOP package (600 mW at no air flow). See

Figure 5 .

(5)

50000 cycles.

(6)

Jitter depends on configuration. Jitter data is for normal tr/tf, input frequency = 27 MHz, f(VCO) = 147 MHz output.

(7)

The tsk(o) specification is only valid for equal loading of all outputs.

6

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