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CD54HCT74F Datasheet(PDF) 3 Page - Texas Instruments |
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CD54HCT74F Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 28 page ![]() 5 Pin Configuration and Functions 1 2 3 7 4 5 6 14 13 12 8 11 10 9 1D 1CLK 1PRE 1Q 1Q GND 2CLR 2D 2CLK 2PRE 2Q VCC 2Q 1CLR Figure 5-1. D, N, or J Package 14-Pin SOIC, PDIP, or CDIP Top View Pin Functions PIN I/O DESCRIPTION NAME NO. 1 CLR 1 Input Channel 1, Clear Input, Active Low 1D 2 Input Channel 1, Data Input 1CLK 3 Input Channel 1, Positive edge triggered clock input 1 PRE 4 Input Channel 1, Preset Input, Active Low 1Q 5 Output Channel 1, Output 1 Q 6 Output Channel 1, Inverted Output GND 7 — Ground 2 Q 8 Output Channel 2, Inverted Output 2Q 9 Output Channel 2, Output 2 PRE 10 Input Channel 2, Preset Input, Active Low 2CLK 11 Input Channel 2, Positive edge triggered clock input 2D 12 Input Channel 2, Data Input 2 CLR 13 Input Channel 2, Clear Input, Active Low VCC 14 — Positive Supply www.ti.com CD74HCT74, CD54HCT74 SCHS409 – JUNE 2020 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 3 |
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