CDx4HCT74 Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset

1 Features

• LSTTL input logic compatible

– VIL(max) = 0.8 V, VIH(min) = 2 V

• CMOS input logic compatible

– II ≤ 1 µA at VOL, VOH

• Buffered inputs

• 4.5 V to 5.5 V operation

• Wide operating temperature range:

-55°C to +125°C

• Supports fanout up to 10 LSTTL loads

• Significant power reduction compared to LSTTL

logic ICs

2 Applications

• Convert a momentary switch to a toggle switch

• Divide a clock signal by 2 or 4

3 Description

The

CDx4HCT74-Q1

devices

contain

two

independent D-type positive-edge-triggered flip-flops

with asynchronous preset and clear pins for each.

Device Information(1)

PART NUMBER

PACKAGE

BODY SIZE (NOM)

CD74HCT74M

SOIC (14)

8.70 mm × 3.90 mm

CD74HCT74E

PDIP (14)

19.30 mm × 6.40 mm

CD54HCT74F

CDIP (14)

21.30 mm × 7.60 mm

(1)

For all available packages, see the orderable addendum at

the end of the data sheet.

xCLK

C

xD

C

C

C

C

xQ

C

xPRE

xQ

xCLR

C

C

C

C

Functional block diagram

CD74HCT74, CD54HCT74

SCHS409 – JUNE 2020

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.