ISO7320C, ISO7320FC, ISO7321C, ISO7321FC

SLLSEK8C – JANUARY 2015 – REVISED APRIL 2015

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Typical Application (continued)

9.2.1 Design Requirements

9.2.1.1 Typical Supply Current Equations

ISO7320:

ISO7321:

At VCC1 = VCC2 = 5 V

At VCC1 = VCC2 = 5 V

•

ICC1 = 0.3838 + (0.0431 x f)

•

ICC1 and ICC2 = 1.5877 + (0.066 x f) + (0.00123 x f x CL)

•

ICC2 = 2.74567 + (0.08433 x f) + (0.01 x f x CL)

At VCC1 = VCC2 = 3.3 V

At VCC1 = VCC2 = 3.3 V

•

ICC1 = 0.2394 + (0.02355 x f)

•

ICC1 and ICC2 = 1.187572 + (0.019399 x f) + (0.0019029 x

f x CL)

•

ICC2 = 2.10681 + (0.04374 x f) + (0.007045 x f x CL)

ICC1 and ICC2 are typical supply currents measured in mA, f is data rate measured in Mbps, CL is the capacitive

load measured in pF.

9.2.2 Detailed Design Procedure

9.2.2.1 Electromagnetic Compatibility (EMC) Considerations

Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge

(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances

are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level

performance and reliability depends, to a large extent, on the application board design and layout, the ISO732x

incorporate many chip-level design improvements for overall system robustness. Some of these improvements

include:

•

Robust ESD protection cells for input and output signal pins and inter-chip bond pads.

•

Low-resistance connectivity of ESD cells to supply and ground pins.

•

Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.

•

Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance

path.

•

PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic

SCRs.

•

Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.

9.2.3 Application Performance Curves

Typical eye diagrams of ISO732x below indicate low jitter and wide open eye at the maximum data rate of 25

Mbps.

Figure 19. Eye Diagram at 25 Mbps, 3.3 V and 25°C

Figure 18. Eye Diagram at 25 Mbps, 5 V and 25°C

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