Document No. 008-0250-0

Page 3 - 3

Rev. I

Model 636

5.0mm x 3.2mm Low Cost

HCMOS/TTL Clock Oscillator

ELECTRICAL CHARACTERISTICS

LVCMOS OUTPUT WAVEFORM

TEST CIRCUIT, CMOS LOAD

ENABLE TRUTH TABLE

MECHANICAL SPECIFICATIONS

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNIT

Enable Function

Enable Input Voltage

Model 636M

Pin 1 Logic '1', Output Enabled

1.26

-

-

Model 636N

Pin 1 Logic '1', Output Enabled

1.75

-

-

Model 636L

Pin 1 Logic '1', Output Enabled

2.0

-

-

Model 636S

Pin 1 Logic '1', Output Enabled

4.0

-

-

Disable Input Voltage

Model 636M,636N,636L

Pin 1 Logic '0', Output Disabled

-

-

0.3

Model 636S

Pin 1 Logic '0', Output Disabled

-

-

0.8

Enable Time (M,N,L,S)

TPLZ

Pin 1 Logic '1'

-

-

10

ms

Standby Current

IST

Pin 1 Logic '0', Output Disabled

-

-

10

µA

V

VIL

VIH

MARKING INFORMATION

1. ** - Manufacturing Site Code.

2. YWW – Date code, Y – year, WW – week.

3. XXXMXXXX – Frequency is marked with only

leading significant digits before the ‘M’ and 4 digits

after the ‘M’ [including zeros].

Ex. XXMXXXX [62M5000]

XXXMXXXX [155M5200]

PACKAGE DRAWING

NOTES

1. JEDEC termination code (e4). Barrier-plating is

nickel [Ni] with gold [Au] flash plate.

2. Reflow conditions per JEDEC J-STD-020, +260°C

maximum, 20 seconds.

3. MSL = 1.

SUGGESTED SOLDER PAD GEOMETRY

CBYPASS should be ≥ 0.01 uF.

D.U.T. PIN ASSIGNMENTS

PIN

SYMBOL

DESCRIPTION

1

EOH

Enable

2

GND

Circuit & Package Ground

3

Output

RF Output

4

VCC

Supply Voltage

PIN 1

PIN 3

Logic ‘1’

Output

Open

Output

Logic ‘0’

High Imp.

CTS**YWW

● XXXMXXXX