LP3921 datasheet(15/44 Pages) TI2

15 / 44 page

PS_HOLD

RESET

1.2s

HF_PWR

CHG_IN

320 ms

PS_HOLD needs to be asserted within 1200 ms after

CHG_IN or HF_PWR rising edge has been detected.

(HF_PWR level detected for LP3921)

Note: Serial I/F commands only take place

after PS_HOLD is asserted.

PS_HOLD high < 1.2s from I/P detection

If charger is connected (CHG_IN) or HF_PWR is

applied, then both events are filtered for 320 ms

before enabling LDO1

Debounce time before normal start up sequence, 320 ms.

60 ms

87% Reg

C Control

< 200 Ps

LDO4,5,6

LDO7

LDO3

LDO2

LDO1

RX_EN, TX_EN,

TCXO_EN

LP3921

www.ti.com

SNVS580A – AUGUST 2008 – REVISED MAY 2013

Figure 3. Device Power Up Logic Timing: CHG_IN, HF_PWR

START UP

Device start is initiated by any of the 3 input signals, PWR_ON, HF_PWR and CHG_IN.

PWR_ON

When PWR_ON goes high the device will remain powered up, a PS_HOLD applied will allow the device to

remain powered after the PWR_ON signal has gone low.

HF_PWR, CHGIN

PS_HOLD needs to be asserted within 1200 ms after a CHG_IN or HF_PWR rising edge has been detected. For

applications where a level sensitive input is required the LP3921 is available with a level detect input at

HF_PWR.

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