The circuit accepts single-ended or differential input signals. The PGA848 operates with independent input and

output power supplies. In this example, ±15V power supplies power the input stage, and a unipolar 5.3V supply

powers the output stage. The PGA848 output stage supply is powered by the same 5.3V ADC supply. The 5.3V

output supply operation prevents overloading the ADC inputs during PGA overdrive conditions. The REF6250

is selected as the ADC voltage reference. The REF6250 is a low-noise, low-drift, precision, 5V reference

connected to the ADS8860 reference input ADC REFIN pin.

The PGA848 output voltage is developed with respect to the REF pin. The REF pin is set to the SAR ADC

midscale voltage by dividing the REF6250 ADC reference with a precision resistive voltage divider. The OPA192

buffer drives the PGA848 REF pin. The OPA192 is a precision amplifier with low offset, low drift, and 10MHz

bandwidth.

8.2.1.1 Design Requirements

Table 8-1 lists the design requirements for the application driving the ADS8860 ADC.

Table 8-1. Design Parameters

PARAMETER

VALUE

Supply voltages

VS± = ±15V, VLVDD = 5.3V, VLVSS = GND, ADC REFIN = 5V

PGA848 reference pin

VREF = 2.5V

Full-scale range of the ADC

FSR = 5V

Sampling rate of the ADC

fSAMPLE = 1MSPS

Signal frequency

1kHz

RC kickback filter

RFIL = 15Ω, CDIFF = 1.2nF, CCM = 120pF

8.2.1.2 Detailed Design Procedure

The first filter located at the input of the PGA (see Figure 8-5) helps reduce electromagnetic interference

(EMI) and radio frequency interference (RFI), high-frequency, extrinsic noise. Customize this filter as per the

application bandwidth and antialiasing requirements.

The second filter is provided by CFB in parallel with the PGA 6.67kΩ feedback resistors. The PGA resistors

are ±15% absolute tolerance, as such, consider the effect of the tolerance on the filter cutoff frequency. CFB =

75pF results in a filter cutoff frequency of 318kHz. On the high side of the resistor tolerance, the filter frequency

changes to 277kHz. The device allows for flexibility to modify the CFB capacitor value to adjust bandwidth, with a

trade-off on the broadband noise of the circuit.

The third filter placed at the ADS8860 inputs works as a charge reservoir filter to drive the SAR ADC. The

charge kickback filter reduces the instantaneous charge demand of the amplifier, maintaining low distortion that

otherwise potentially degrades because of incomplete ADC sample-and-hold settling. The RC filter combination

(RFIL, CDIFF) is tuned for ADC sample-and-hold settling and total harmonic distortion (THD) performance, while

maintaining stability of the PGA. High-grade C0G capacitors are used everywhere in the signal path for the low

distortion properties.

The PGA848 front end, accounting for all three filters, provides a nominal f–3dB bandwidth of 318kHz. On the

high side of the internal 6.67kΩ feedback resistor tolerance, the PGA848 f–3dB bandwidth changes to 277kHz.

However, the circuit maintains –0.1dB flatness to 41kHz.

The ADS8860 requires a full-scale input in the range of 0V to the 5V ADC reference. The PGA848 REF pin is set

to a nominal voltage of 2.5V to shift the signal to the ADC midscale voltage.

Generate the PGA848 REF voltage by feeding the REF6250 5V reference through a 10kΩ-to-10kΩ precision

voltage divider implemented with ±0.05% tolerance, low-drift ±5ppm/°C resistors. Drive the PGA848 REF pin

with a low-impedance source. Use an op amp such as the OPA192 as a buffer to drive the REF pin.

The OPA192 buffer is configured in a dual-feedback configuration to provide stability while driving the REF pin

and 22nF bypass capacitor. RISO is a 20Ω isolation resistor that provides separation of two feedback paths for

optimized stability. The first feedback path through the feedback resistor, RF = 2kΩ, connected directly to the

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