REF pin. The second feedback path is through the feedback capacitor, CF = 2nF, connected to the output of

the op amp. The circuit provides a loop gain phase margin of 86°. The noninverting input of the OPA192 buffer

has a low-pass filter with R = 1kΩ, C = 10nF to reduce the resistive divider thermal noise. Using any other load

capacitance requires recalculation of the stability components: RF, CF, and RISO. If modifying the REF bypass

capacitance, verify the circuit is stable with simulation using the OPA192 TINA-TI model (or PSpice®-for-TI

model). Confirm the circuit provides more than 60° of phase margin.

8.3 Power Supply Recommendations

The nominal performance of the PGA848 is specified with input-stage supply and output-stage supply voltages

of ±15V, and VICM and VREF at mid-supply. Within the specified limits, custom input common-mode and output

common-mode voltages are usable without compromising performance; see also Section 6.3. To prevent

damage to internal circuitry, the output-stage power supplies are clamped to stay within the input-stage supply

voltage levels; see also Section 7.2.

CAUTION

Supply voltages higher than 40V (±20V) permanently damage the device.

8.4 Layout

8.4.1 Layout Guidelines

Attention to good layout practices is always recommended. For best operational performance of the device, use

good PCB layout practices, including:

• To avoid converting common-mode signals into differential signals and thermal electromotive forces (EMFs),

verify both input paths are symmetrical and well-matched for source impedance and capacitance.

• Noise potentially propagates into analog circuitry through the power pins of the device and of the circuit as a

whole. Bypass capacitors reduce the coupled noise by providing low-impedance power sources local to the

analog circuitry.

– Connect low-ESR, 0.1µF ceramic bypass capacitors between each supply pin and ground, placed as

close as possible to the device. A single bypass capacitor from V+ to ground is applicable for single-

supply applications.

• To reduce parasitic coupling, run the input traces as far away as possible from the supply or output traces.

If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better than in

parallel with the noisy trace.

• Leakage on the DA_IN+ and DA_IN– pins potentially causes dc offset errors in the output voltages.

Additionally, excessive parasitic capacitance at these pins potentially results in decreased phase margin

and affects the stability of the output stage. If these pins are not used to implement deliberate capacitive

feedback, follow best practices to minimize leakage and parasitic capacitance.

• Follow best practices to minimize leakage and parasitic capacitance, which includes implementing keep-out

areas in any ground planes located immediately below the input pins.

• Minimize the number of thermal junctions. If possible, route the signal path using a single layer without vias.

• Keep sufficient distance from major thermal energy sources (circuits with high power dissipation). If not

possible, place the device so that the thermal energy source effects on both sides of the differential signal

path are evenly matched.

• Keep the traces as short as possible.

PGA848

SBOSAN4 – AUGUST 2025

www.ti.com

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