ADS800

2

SBAS035B

www.ti.com

ADS800U

PARAMETER

CONDITIONS

TEMP

MIN

TYP

MAX

UNITS

ELECTRICAL CHARACTERISTICS

At TA = +25°C, VS = +5V, Sampling Rate = 40MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted.

ABSOLUTE MAXIMUM RATINGS(1)

+V

S ....................................................................................................... +6V

Analog Input .............................................................. 0V to (+V

S + 300mV)

Logic Input ................................................................ 0V to (+V

S + 300mV)

Case Temperature ......................................................................... +100

°C

Junction Temperature .................................................................... +150

°C

Storage Temperature ..................................................................... +125

°C

External Top Reference Voltage (REFT) .................................. +3.4V Max

External Bottom Reference Voltage (REFB) .............................. +1.1V Min

NOTE: (1) Stresses above these ratings may permanently damage the device.

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas

Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper han-

dling and installation procedures can cause damage.

ESD damage can range from subtle performance degrada-

tion to complete device failure. Precision integrated circuits

may be more susceptible to damage because very small

parametric changes could cause the device not to meet its

published specifications.

Resolution

12

Bits

Specified Temperature Range

TAMBIENT

0

+70

°C

Operating Temperature Range

TAMBIENT

–40

+85

°C

ANALOG INPUT

Differential Full-Scale Input Range

Both Inputs,

+1.25

+3.25

V

180

° Out-of-Phase

Common-Mode Voltage

+2.25

V

Analog Input Bandwidth (–3dB)

Small-Signal

–20dBFS(1) Input

+25

°C

400

MHz

Full-Power

0dBFS Input

+25

°C65

MHz

Input Impedance

1.25 || 4

M

Ω || pF

DIGITAL INPUT

Logic Family

TTL/HCT Compatible CMOS

Convert Command

Start Conversion

Falling Edge

ACCURACY(2)

fS = 2.5MHz

Gain Error

+25

°C

±0.4

±1.5

%

Full

±0.6

±2.5

%

Gain Drift

±95

ppm/

°C

Power-Supply Rejection of Gain

∆ +V

S = ±5%

+25

°C

0.01

0.15

%FSR/%

Input Offset Error

Full

±2.6

±3.5

%

Power-Supply Rejection of Offset

∆ +V

S = ±5%

+25

°C

0.02

0.15

%FSR/%

CONVERSION CHARACTERISTICS

Sample Rate

10k

40M

Sample/s

Data Latency

6.5

Convert Cycle

DYNAMIC CHARACTERISTICS

Differential Linearity Error

f = 500kHz

tH = 13ns(3)

+25

°C

±0.6

±1.0

LSB

Full

±0.8

LSB

f = 12MHz

+25

°C

±0.4

±1.0

LSB

Full

±0.5

LSB

No Missing Codes

tH = 13ns(3)

+25

°C

Tested

LSB

Integral Linearity Error at f = 500kHz

Full

±1.9

LSB

Spurious-Free Dynamic Range (SFDR)

f = 500kHz (–1dBFS input)

+25

°C

65

72

dBFS

Full

60

66

dBFS

f = 12MHz (–1dBFS input)

+25

°C58

61

dBFS

Full

55

61

dBFS

SPECIFIED

PACKAGE

TEMPERATURE

PACKAGE

ORDERING

TRANSPORT

PRODUCT

PACKAGE-LEAD

DESIGNATOR

RANGE

MARKING

NUMBER

MEDIA, QUANTITY

ADS800U

SO-28

DW

–40

°C to +85°C

ADS800U

ADS800U

Rails, 28

NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at

www.ti.com.

PACKAGE/ORDERING INFORMATION(1)

NOTES: (1) dBFS refers to dB below Full-Scale. (2) Percentage accuracies are referred to the internal A/D converter Full-Scale Range of 4Vp-p. (3) To assure

DNL and no missing code performance, see timing diagram footnote 2. (4) IMD is referred to the larger of the two input signals. If referred to the peak envelope

signal (

≈0dB), the intermodulation products will be 7dB lower. (5) No “rollover” of bits.