ADS800

4

SBAS035B

www.ti.com

PIN CONFIGURATION

Top View

SO

PIN

DESIGNATOR

DESCRIPTION

1

GND

Ground

2

B1

Bit 1, Most Significant Bit

3

B2

Bit 2

4

B3

Bit 3

5

B4

Bit 4

6

B5

Bit 5

7

B6

Bit 6

8

B7

Bit 7

9

B8

Bit 8

10

B9

Bit 9

11

B10

Bit 10

12

B11

Bit 11

13

B12

Bit 12, Least Significant Bit

14

GND

Ground

15

+VS

+5V Power Supply

16

CLK

Convert Clock Input, 50% Duty Cycle

17

+VS

+5V Power Supply

18

OE

HI: High Impedance State. LO or Floating: Nor-

mal Operation. Internal pull-down resistors.

19

MSBI

Most Significant Bit Inversion, HI: MSB inverted

for complementary output. LO or Floating: Straight

output. Internal pull-down resistors.

20

+VS

+5V Power Supply

21

REFB

Bottom Reference Bypass. For external bypass-

ing of internal +1.25V reference.

22

CM

Common-Mode Voltage. It is derived by (REFT +

REFB)/2.

23

REFT

Top Reference Bypass. For external bypassing

of internal +3.25V reference.

24

+VS

+5V Power Supply

25

GND

Ground

26

IN

Input

27

IN

Complementary Input

28

GND

Ground

PIN DESCRIPTIONS

GND

B1

B2

B3

B4

B5

B6

B7

B8

B9

B10

B11

B12

GND

GND

IN

IN

GND

+V

S

REFT

CM

REFB

+V

S

MSBI

OE

+V

S

CLK

+V

S

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

ADS800

TIMING DIAGRAM

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

tCONV

Convert Clock Period

25

100

µsns

tL

Clock Pulse LOW

12

12.5

ns

tH

Clock Pulse HIGH

12(2)

12.5

ns

tD

Aperture Delay

2

ns

t1

Data Hold Time, CL = 0pF

3.9

ns

t2

New Data Delay Time, CL = 15pF max

12.5

ns

NOTES: (1) “

” indicates the portion of the waveform that will stretch out at slower sample rates.

(2) tH must be 13ns minimum if no missing codes is desired only for the conditions of tCONV ≤ 28ns

and fIN < 2MHz.

Track

Hold

“N”

Hold

“N + 1”

Hold

“N + 2”

Hold

“N + 3”

Hold

“N + 4”

Hold

“N + 5”

Hold

“N + 6”

Track

Data Valid

N – 7

Data Valid

N – 6

Internal

Track-and-Hold

Convert

Clock

Output

Data

t

D

t

2

t

1

DATA LATENCY

(6.5 Clock Cycles)

t

CONV

t

L

t

H

Track

Track

Track

Track

N – 3

N – 5N – 4N – 2N – 1

N

Track

Track

Data Valid

N – 8

(1)

Data Invalid