MB85R1001A

DS501-00003-6v1-E

3



BLOCK DIAGRAM



FUNCTIONAL TRUTH TABLE

Note: L = VIL, H = VIH, X can be either H, L,

or

, Hi-Z = High Impedance

: Latch address and latch data at falling edge,

: Latch address and latch data at rising edge

*1 : OE control of the Pseudo-SRAM means the valid address at the falling edge of OE to read.

*2 : WE control of the Pseudo-SRAM means the valid address and data at the falling edge of WE to write.

Operation Mode

CE1

CE2

WE

OE

I/O1 to I/O8

Supply Current

Standby Precharge

H

X

X

X

Hi-Z

Standby

(ISB)

X

L

X

X

X

X

H

H

Read

H

H

L

Data Output

Operation

(IDD)

L

Read

(Pseudo-SRAM, OE control*1)

L

H

H

Write

H

L

H

Data Input

L

Write

(Pseudo-SRAM, WE control*2)

L

H

H

I/O8

I/O1

A0

A16

FeRAM Array

131,072 x 8

Column Decoder

S/A

I/O1 to I/O8

CE2

WE

OE

CE1

intOE

intWE