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ADS7041IDCUT Datasheet(PDF) 21 Page - Texas Instruments |
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ADS7041IDCUT Datasheet(HTML) 21 Page - Texas Instruments |
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21 / 43 page ![]() 1 2 3 4 11 12 SCLK(fCLK-CAL) CS Sample N 0 0 D9 D8 SDO Data for Sample N D1 D0 16 18 17 32 31 Sample N+1 tCONV tCAL tACQ tPH_CS tSU_CSCK tD_CKCS ADS7041 www.ti.com SBAS675C – NOVEMBER 2014 – REVISED DECEMBER 2015 8.4.1.2 Offset Calibration During Normal Operation Offset calibration can be done during normal device operation if at least 32 SCLK falling edges are provided in one serial transfer frame. During the first 12 SCLKs, the device converts the sample acquired on the CS falling edge and provides data on the SDO output. The device initiates the offset calibration on the 17th SCLK falling edge and calibration completes on the 32nd SCLK falling edge. The SDO output remains low after the 12th SCLK falling edge and SDO goes to 3-state after CS goes high. If the device is provided with less than 32 SCLKs during a serial transfer frame, the OCR is not updated. Table 3 provides the timing parameters for offset calibration during normal operation. For subsequent samples, the device adjusts the conversion results with the value stored in the OCR. The conversion result adjusted with the value stored in the OCR is provided by the device on the SDO output. Figure 38 shows the timing diagram for offset calibration during normal operation. Table 3. Offset Calibration During Normal Operation MIN TYP MAX UNIT fCLK-CAL SCLK frequency for calibration for 2.25 V < AVDD < 3.6 V 14 MHz fCLK-CAL SCLK frequency for calibration for 1.65 V < AVDD < 2.25 V 12 MHz tCAL Calibration time during normal operation 15 tSCLK ns tACQ Acquisition time 235 ns tPH_CS CS high time tACQ ns tSU_CSCK Setup time: CS falling to SCLK falling 15 ns tD_CKCS Delay time: last SCLK falling to CS rising 10 ns Figure 38. Offset Calibration During Normal Operation Timing Diagram Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 21 Product Folder Links: ADS7041 |
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