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ADS9128RHAR Datasheet(PDF) 49 Page - Texas Instruments |
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ADS9128RHAR Datasheet(HTML) 49 Page - Texas Instruments |
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49 / 67 page ![]() 7.3 Register Bank 2 Figure 7-53. Register Bank 2 Map ADD D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1Ch RESERVED CLK6 RESERVED Table 7-3. Register Section/Block Access Type Codes Access Type Code Description R R Read W W Write R/W R/W Read or write Reset or Default Value -n Value after reset or the default value 7.3.1 Register 1Ch (offset = 1Ch) [reset = 0h] Figure 7-54. Register 1Ch 15 14 13 12 11 10 9 8 RESERVED R/W-0h 7 6 5 4 3 2 1 0 CLK6 RESERVED R/W-0h R/W-0h Figure 7-55. Register 1Ch Field Descriptions Bit Field Type Reset Description 15-8 RESERVED R/W 0h Reserved. Do not change from the default reset value. 7-6 CLK6 R/W 0h Clock configuration for ADS9127. See the Data Interface section for details. Not applicable for the ADS9129 and ADS9128. 0 : 24-bit 2-lane mode 3 : All other modes 5-0 RESERVED R/W 0h Reserved. Do not change from the default reset value. www.ti.com ADS9127, ADS9128, ADS9129 SBASB82 – MAY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 49 Product Folder Links: ADS9127 ADS9128 ADS9129 |
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