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FEATURES

APPLICATIONS

SYSTEM BLOCK DIAGRAM

GC5322

DUC–CFR–DPD

Baseband

Input

DAC

C672x

DSP

DAC

I/Q

ADC

I/Q

Modulator

LO

Mixer

LPA

HPA

B0278-01

DAC5682Z

CDCM7005

ADS5444

THS9001

TRF3761

TRF3703

DESCRIPTION

GC5322

SLWS208 – JANUARY 2008

www.ti.com

GC5322 Wideband Digital Predistortion Transmit Processor

• 1.2-V Core, 3.3-V I/O

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• Integrated DUC, CFR, and DPD Functions

• Typical Power Consumption = 2.5 W

• Up to 40-MHz Combined Signal Bandwidth

• Flexible DSP Algorithm Supports Existing and

Emerging Wireless Standards

• DUC: up to 12 CDMA2000 or TD-SCDMA, 4

W-CDMA, 4–10 MHz or 2–20 MHz OFDMA

• Supports Direct Interface to TI High-Speed

Carriers

Data Converters

• CFR: Typically Meets 3GPP TS 25.141 <6.5 dB

PAR, <8 dB PAR for 802.16e Signals

• 3GPP (W-CDMA, TD-SCDMA) Base Stations

• DPD: Memory Compensation, Typical ACLR

• 3GPP2 (CDMA2000) Base Stations

Improvement of 20 dB to 30 dB or More

• WiMAX and WiBRO (OFDMA) Base Stations

• Transmit- and Feedback-Channel Equalizers

• Multicarrier Power Amplifiers (MCPAs)

• 352-Ball S-PBGA Package, 27 mm × 27 mm

The GC5322 is a wideband digital predistortion transmit processor that includes a digital upconverter (DUC)

block, a crest factor reduction (CFR) block, and a digital predistortion (DPD) block with its associated feedback

chain and capture buffers. The GC5322 processes composite input bandwidths of up to 40 MHz and processes

DPD sample rates of up to 140 MHz. The GC5322 DUC block accepts baseband signals over an interleaved

parallel interface at a data rate of up to 93.3 MSPS. The GC5322 CFR block reduces the peak-to-average ratio

(PAR) of wideband digital signals provided in quadrature (I/Q) format, such as those used in third-generation

(3G) code division multiple access (CDMA) wireless and orthogonal frequency division multiple access (OFDMA)

applications. The GC5322 DPD block reduces adjacent-channel leakage ratio (ACLR), or out-of-band energy, by

20 dB to 30 dB or more. The efficiency of follow-on power amplifiers (PAs) is substantially improved by reducing

the PAR and ACLR of digital signals. The digital-to-RF conversion can be further simplified by the fractional

interpolator between the CFR and the DPD blocks, and a bulk upconverter (BUC) in the final stage of the

GC5322. This feature typically eliminates the need for superheterodyne (dual-stage) upconversion architectures.

Transmit and feedback NCO/mixers provide additional flexibility in the system frequency planning.

To request more information on the GC5322 Wideband Digital Pre-Distortion Transmit Processor, go to

http://www.ti.com/gc5322-info.

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

TMS320C64x, 'C55x, 'C64x are trademarks of Texas Instruments.

3

All other trademarks are the property of their respective owners.

ADVANCE INFORMATION concerns new products in the sampling

Copyright © 2008, Texas Instruments Incorporated

or preproduction phase of development. Characteristic data and

other specifications are subject to change without notice.