CDx4HC138, CDx4HCT138, CDx4HC238, CDx4HCT238 High-Speed CMOS Logic 3- to

8-Line Decoder/Demultiplexer Inverting and Noninverting

1 Features

• Select one of eight data outputs:

– Active low for '138

– Active high for '238

• l/O port or memory selector

• Three enable inputs to simplify cascading

• Typical propagation delay of 13 ns at VCC = 5 V, CL

= 15 pF, TA = 25°C

• Fanout (over temperature range)

– Bus driver outputs: 15 LSTTL loads

– Standard outputs: 10 LSTTL loads

• Wide operating temp range: -55°C to 125°C

• Balanced propagation delay and transition times

• Significant power reduction compared to LSTTL

logic ICs

• HC types

– 2 V to 6 V operation

– High noise immunity: NIL = 30%, NIH = 30% of

VCC at VCC = 5 V

• HCT types

– 4.5-V to 5.5-V operation

– Direct LSTTL input logic compatibility, VIL= 0.8

V (Max), VIH = 2 V (Min)

– CMOS input compatibility, Il ≤ 1µA at VOL, VOH

A

0

A

1

A

2

OUTPUT

ENABLE

Y

0

Y

1

Y

2

G

1

G

2

Y

3

Y

4

Y

5

Y

6

Y

7

G

0

3:8 DECODER

000

001

010

011

100

101

110

111

Functional Block Diagram '138

2 Description

The CDx4HC(T)138 and '238 are three to eight

decoders with one standard output strobe (G2) and

two active low output strobes (G 1 and G 0). When the

outputs are gated by any of the strobe inputs, they are

all forced into the high state. When the outputs are not

disabled by the strobe inputs, only the selected output

is low while all others are high.

The CDx4HC(T)238 is a three to eight decoder with

one standard output strobe (G2) and two active low

output strobes (G 1 and G 0). When the outputs are

gated by any of the strobe inputs, they are all forced

into the low state. When the outputs are not disabled

by the strobe inputs, only the selected output is high

while all others are low.

Device Information

PART NUMBER

PACKAGE

(1)

BODY SIZE (NOM)

CD74HC138E

PDIP (16)

25.40 mm × 6.35 mm

CD74HCT138E

PDIP (16)

25.40 mm × 6.35 mm

CD74HCT238E

PDIP (16)

25.40 mm × 6.35 mm

CD74HC138M

SOIC (16)

9.90 mm × 3.90 mm

CD74HCT238M

SOIC (16)

9.90 mm × 3.90 mm

CD74HC238NS

SO (16)

10.20 mm × 5.30 mm

CD74HC238PW

TSSOP (16)

5.00 mm × 4.40 mm

CD74HCT238PW

TSSOP (16)

5.00 mm × 4.40 mm

CD54HC138F

CDIP (16)

21.34 mm × 6.92 mm

CD54HCT138F

CDIP (16)

21.34 mm × 6.92 mm

CD54HCT238F

CDIP (16)

21.34 mm × 6.92 mm

(1)

For all available packages, see the orderable addendum at

the end of the data sheet.

CD54HC138, CD74HC138, CD54HCT138, CD74HCT138, CD54HC238, CD74HC238, CD54HCT238,

CD74HCT238

SCHS147J – NOVEMBER 1998 – REVISED NOVEMBER 2021

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.