L5965 datasheet(17/73 Pages) STMICROELECTRONICS

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Functional description

4.1

Programming by OTP

OTP cells are used to program all regulators output voltages and run frequencies, together with additional device

features. Programmable values are:

•

BUCK1 output values : 5.0 V, 3.8 V, 3.3 V, 1.8 V, 1.2 V, 1.1 V, 1.0 V or 0.8 V (3 bits)

•

BUCK2 output values : 5.0 V, 3.6 V, 3.3 V, 1.5 V, 1.35 V, 1.2 V, 1.1 V or 1.0 V (3 bits)

•

BUCK2 current limit value: 1.35 A or 2.6 A (1 bit)

•

BUCK2 free running frequency: 0.4 or 2.4 MHz (1 bit)

•

BUCK3 output values : 3.3 V, 2.5 V, 2.3 V, 2.0 V, 1.8 V, 1.35 V, 1.2 V, or 1.0 V (3 bits)

•

BUCK4 output values : 3.3 V, 1.8 V, 1.35 V, 1.3 V, 1.25 V, 1.2 V, 1.12 V or 1.1 V (3 bits)

•

LDO output values : 5.0 V, 3.3 V, 2.8 V, 2.5 V, 1.8 V, 1.3 V, 1.25 V or 1.2V (3 bits)

•

LDO output current limitation: 300 or 600 mA (1 bit)

•

BOOST output voltage: 7.0 V or 5.0 V (1 bit)

•

VREF output voltage: 4.1 V, 3.3 V, 2.5 V or 1.8 V (2 bits)

•

Watchdog selection: by WDI pin or through SPI (2 bits)

–

if OTP "WD_cfg" bits is "00" or "01": Use watchdog;

–

if OTP "WD_cfg" bits is "10" : No watchdog;

–

if OTP "WD_cfg" bits is "11": Use SPI as watchdog;

•

Effect of WD failure on FSM. If SPI_WD_REC_en=0 and OTP_WD_REC_en=0, a WD failure asserts

RESET_B but not FSM: the device keeps active state with regulators running. If one of these bits is “1”,

RESET_B is asserted and FSM goes to REC state.

•

Main BUCK selection: BUCK1 or BUCK2 (3 bit)

•

Other regulators turning on order: from the second to the seventh one (3 bits per each regulator)

•

Regulators turning on delay after Power Good of the previous regulator: 0, 2, 5 or 10 ms (2 bits)

•

Reset activation after Power Good signal of a specific regulator (3 bits), with the possibility to add a delay

from 0 (no delay) to 10 ms (2 bits)

•

Reset activation by the over-voltage of regulators in reset activation list (1 bit)

The step in which the reset is released (OTP Line 8 Bit15:13) at power-up defines the reset activation list. All the

regulators turned on before the reset is released are part of the reset activation list and the faults on these

controllers affect the status of the device as described in the specific chapters. For example, setting OTP Line 8

Bit15:13 equal to "001" means that the main regulator and the 2nd regulator are part of the reset activation list.

The others, if present, starting as 3rd or 4th and so on are not in the reset activation list.

The approach used in the L5965 device is the following:

•

L5965 OTP cells must be programmed before the first device turning on:

–

No default status is present for OTP programmed parameters

–

Customer can program OTP by himself

•

If all OTP cells are not written, the device automatically moves to OTP program mode.

•

OTP programming can be done only one time:

–

It is not possible an additional writing procedure after the first one:

◦

3 bits stored inside OTP means OTP written (USR Area Protection)

–

If the OTP programming procedure fails or it is wrong, the device is discarded

If a regulator is not used (disabled), it is recommended to set to “0” its enable and SeqId (post regulator

activation) bits. PGNDx, VREGx_S and VBOOST_S pins should be connected to ground, while other pins can be

left floating. If the internal VREG is not used, EXSUP pin should be connected to ground.

L5965

Functional description

DS12567 - Rev 3

page 17/73

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