L5965 datasheet(26/73 Pages) STMICROELECTRONICS

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Figure 13. Fault function in active mode

GADG1105180907PS

NOR

FAULT pin

‘1’: no fault

‘0’: with fault

VBAT1/VBAT2_uv/ov

(read&clear)

All_buck_fault

(read&clear)

Watchdog_fail

(read&clear)

SPI_parity_fail

(read&clear)

LBIST_err

PowerUp_fault

Vreg_nok

Center_ot

Vreg_ot

Vref_uv/ov/oc

Ldo_uv/ov/ot

Boost_uv/ov/oc/ot/pg_loss

Buck1/2_uv/ov/oc/ot/pg_loss

In order to avoid triggering RESET and FAULT during the soft start time, the UV is masked when regulators

(BUCK1//3/4, BOOST, LDO and VREF) are going to be enabled. The masking time is given by the following table.

Table 7. UV masking time

Regulator

Masking time (ms typ.)

BUCK1

BUCK2

BUCK3

BUCK4

BOOST

VREF

0.5

LDO

0.5

VREG

0.5

4.2.13

Configurable watchdog and reset

During normal operation, the watchdog monitors the microcontroller within a programmable trigger cycle. When

the device is in ACTIVE mode, which means the power up phase has been correctly performed and RESET_B

signal has been released, the watchdog is started with a timeout (long open window TLW ) to allow the

microcontroller to run its own setup and then to start the window watchdog by setting an inner signal TRIG = 1.

Subsequently, the micro controller has to serve the watchdog by providing the watchdog trigger bit TRIG within

the safe trigger area TSW. The trigger time is configurable by SPI. A correct watchdog trigger signal immediately

starts the next cycle. A wrong watchdog trigger causes a watchdog failure.

WDI signal can be ignored (by setting OTP bit) and SPI can be used as watchdog: in this case, a specific SPI

right time, a watchdog failure happens. In case of a watchdog failure, RESET_B and FAULT pins are always

asserted, and the device goes to REC mode or keeps in ACTIVE mode depending on the WD_REC_en OTP

configuration.

If OTP_WD_REC_en = 1 the device goes to REC mode in case of WD failure, and WD is no more active until the

ACTIVE mode is reached.

If OTP_WD_REC_en = 0, the device keeps in ACTIVE mode in case of WD failure, and WD is inactive for 280 ns

(1 system clock cycle, not significant), then active again in Long open window, and RESET_B asserts a small

pulse (typ 8 µs). Moving SPI_WD_REC_en = 1, the device behavior is the same as OTP_WD_REC_en = 1.

Configuration with OTP_WD_REC_en = 0 is useful if voltages should be immediately active in order to initialize

the system, regardless of the WD signal.

L5965

Voltage regulators and features description

DS12567 - Rev 3

page 26/73

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