L9305 datasheet(105/107 Pages) STMICROELECTRONICS

105 / 107 page

List of tables

Table 1.

PowerSSO-36 and TQFP48 pins list....................................................... 7

Table 2.

Absolute maximum ratings ............................................................. 9

Table 3.

ESD Performance .................................................................. 10

Table 4.

Device operating temperature .......................................................... 10

Table 5.

Global and external supply fault pin error masking ............................................ 11

Table 6.

Solenoid channel and fail safe fault pin error masking.......................................... 12

Table 7.

Digital input/output electrical performance .................................................. 13

Table 8.

VBATP electrical performance .......................................................... 14

Table 9.

Power supply electrical performance ..................................................... 17

Table 10.

Solenoid driver status in hardware mode................................................... 19

Table 11.

PWM period and Frequency Programming ................................................. 20

Table 12.

Solenoid driver channel status in software mode ............................................. 26

Table 13.

INx polarity ....................................................................... 27

Table 14.

LS diagnostic truth table .............................................................. 31

Table 15.

HS diagnostic truth table .............................................................. 31

Table 16.

Valve driver power stage electrical parameters .............................................. 31

Table 17.

Current control electrical parameters ..................................................... 32

Table 18.

Valve driver on state diagnostics parameters ................................................ 33

Table 19.

Valve driver LS off state diagnostics parameters ............................................. 34

Table 20.

Valve Driver HS Off State Diagnostic Parameters............................................. 34

Table 21.

Fail safe predriver electrical parameters ................................................... 36

Table 22.

Safety monitors and self test summary .................................................... 38

Table 23.

VDD Fault Summary ................................................................ 39

Table 24.

VBATP Fault Summary ............................................................... 39

Table 25.

Charge pump fault summary ........................................................... 39

Table 26.

POR fault summary ................................................................. 40

Table 27.

GNDA and GNDD fault summary ........................................................ 40

Table 28.

Solenoid GND fault summary .......................................................... 40

Table 29.

Power supply monitoring electrical performance.............................................. 41

Table 30.

Main and reference oscillator safety parameters ............................................. 42

Table 31.

Oscillator safety switch-off path parameter ................................................. 43

Table 32.

NVM memory map .................................................................. 44

Table 33.

Valve driver safety parameters.......................................................... 45

Table 34.

Core thermal monitoring electrical performance .............................................. 46

Table 35.

SPI time out values ................................................................. 50

Table 36.

Reset latch enable state .............................................................. 50

Table 37.

Time out reset latch counter values ...................................................... 50

Table 38.

SPI electrical parameters ............................................................. 51

Table 39.

SPI page address mapping ............................................................ 52

Table 40.

SPI global page register address mapping ................................................. 52

Table 41.

SPI fault and test page register address mapping............................................. 59

Table 42.

SPI channel page register address mapping ................................................ 71

Table 43.

TQFP48 (7x7x1 mm exp. pad down 5.0x5.0) package mechanical data ............................. 93

Table 44.

PowerSSO-36 (exposed pad down) package mechanical data.................................... 97

Table 45.

Document revision history ............................................................ 100

L9305

List of tables

DS12774 - Rev 10

page 105/107

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