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SPSB100 Datasheet(PDF) 131 Page - STMicroelectronics |
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SPSB100 Datasheet(HTML) 131 Page - STMicroelectronics |
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131 / 213 page  Bit Name Description 0 CRC0 Table 95. DCR7 (0x07) MSB Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 - (R0) 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) RES MASK_LDO1_PG_IRQ MASK_LDO1_PG_TIMEOUT_IRQ MASK_LDO1_IRQ MASK_BOOST_IN_LP_IRQ MASK_BYPASS_VDSMON_IRQ MASK_BOOST_VDSMON_IRQ IRQ_REQUEST Reserved Mask LDO1 PG interrupt bit Mask LDO1 PG timeout interrupt bit Mask LDO1 interrupt bit Mask BOOST in Low power mode interrupt bit Mask bypass VDSMON interrupt bit Mask BOOST VDSMON interrupt bit Interrupt request bit Table 96. DCR7 (0x07) MSB description Bit Name Description 23 RES Reserved 22 MASK_LDO1_PG_IRQ Mask regulator power-good interruption when turned ON through SPI No interrupt generated when turned on by power-up sequence 1: IRQ signal is not generated 0: IRQ signal is generated when the regulator is turned ON through SPI (default) 21 MASK_LDO1_PG_TIMEOUT_IRQ Mask LDO1 power-good timeout when turned on by SPI request No interrupt generated when turned on by power-up sequence 1: IRQ signal is not generated 0: IRQ signal is generated (default) 20 MASK_LDO1_IRQ Mask LDO1 undervoltage interruption 1: IRQ signal is not generated 0: IRQ signal is generated (default) 19 MASK_BOOST_IN_LP_IRQ 1: IRQ masked 0: IRQ not masked 18 MASK_BYPASS_VDSMON_IRQ 1: IRQ masked 0: IRQ not masked 17 MASK_BOOST_VDSMON_IRQ 1: IRQ masked 0: IRQ not masked 16 IRQ_REQUEST 1: Send IRQ to MCU This bit is automatically cleared and always read low 0: No action Table 97. DCR7 (0x07) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) MASK_VS_EW_IRQ RES MASK_CL4_TW_IRQ MASK_CL3_TW_IRQ MASK_CL2_TW_IRQ MASK_CL1_TW_IRQ MASK_CL0_TW_IRQ MASK_OUTHS_IRQ Mask VS early warning interrupt bit Reserved bit Mask current limitation 4 thermal warning interrupt bit Mask current limitation 3 thermal warning interrupt bit Mask current limitation 2 thermal warning interrupt bit Mask current limitation 1 thermal warning interrupt bit Mask current limitation 0 thermal warning interrupt bit Mask out high side interrupt bit Table 98. DCR7 (0x07) description Bit Name Description 15 MASK_VS_EW_IRQ 1: IRQ masked 0: IRQ not masked SPSB100 SPI registers DS14640 - Rev 2 page 131/213 |
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