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SPSB100 Datasheet(PDF) 169 Page - STMicroelectronics |
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SPSB100 Datasheet(HTML) 169 Page - STMicroelectronics |
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169 / 213 page  Table 230. DSR4 (0x24) description Bit Name Description 15 SPI_STATUS_WRT 1: SPI writes access to status register 14 SPI_LBISTED 1: SPI access while SPI is under LBIST test 13 FBB_OV_EW FBB over voltage early warning 1: Indicates the voltage at FBB increased above the FBB over voltage early warning threshold (configured in CR3) In ACTIVE and REC-1 modes, an interrupt pulse is generated at IRQ. Bit is latched until a “read and clear” command 12 FBB_UV_EW FBB under voltage early warning 1: Indicates the voltage at FBB decreased below the FBB under voltage early warning threshold (configured in CR3) In ACTIVE and REC-1 modes, an interrupt pulse is generated at IRQ Bit is latched until a “read and clear” command 11 VS_UV_EW VS early warning 1: Indicates the voltage at VS decreased below the VS early warning threshold (configured in CR3) In ACTIVE and REC-1 modes, an interrupt pulse is generated at IRQ. Bit is latched until a “read and clear” command 10 RES Reserved 9 TW_CL4 Thermal warning of cluster x 1: Indicates cluster x has reached the thermal warning threshold (TSW) Bit is latched until a “read and clear” command 8 TW_CL3 Table 231. DSR4 (0x24) LSB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 (RC1L) 0 (RC1L) 0 (RC1L) 0 (R) 0 (RC1L) 0 (RC1L) 0 (RC1L) 0 (RC1L) TW_CL2 TW_CL1 TW_CL0 TW CRC3 CRC2 CRC1 CRC0 Thermal warning of cluster 2 bit Thermal warning of cluster 1 bit Central thermal warning bit Thermal warning bit Cyclic redundancy checking bit 3 Cyclic redundancy checking bit 2 Cyclic redundancy checking bit 1 Cyclic redundancy checking bit 0 Table 232. DSR4 (0x24) LSB description Bit Name Description 7 TW_CL2 6 TW_CL1 5 TW_CL0 Central thermal warning 4 TW Thermal warning 1: Indicates the temperature has reached the thermal warning threshold (logical OR combination of bits TW_CLx in DSR6) 3 CRC 3 2 CRC 2 1 CRC 1 0 CRC 0 SPSB100 SPI registers DS14640 - Rev 2 page 169/213 |
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