140 Ps (1 conversion)

280 Ps (2 conversions)

TIME (50 Ps /div)

1.1 ms (1 conversion)

2.2 ms (2 conversions)

TIME (500 Ps /div)

28

INA260

SBOS656C – JULY 2016 – REVISED DECEMBER 2016

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Copyright © 2016, Texas Instruments Incorporated

Typical Application (continued)

9.2.2 Detailed Design Procedure

The ALERT pin can be configured to respond to one of the five alert functions described in the ALERT Pin

section. The ALERT pin must be pulled up to the VS pin voltage through an external pullup resistor. The

configuration register is set based on the required conversion time and averaging. The Mask/Enable Register is

set to identify the required alert function and the Alert Limit Register is set to the limit value used for comparison.

9.2.3 Application Curves

Figure 40 shows the ALERT pin response to a bus over voltage limit of 5.5 V for a conversion time (tCT) of 1.1

ms and averaging set to 1. Figure 39 shows the response for the same limit but with the conversion time reduced

to 140 µs. For the scope shots shown in these figures, persistence was enabled on the ALERT channel. This

shows how the ALERT response time can vary depending on when the fault condition occurs relative to the

internal ADC clock of the INA260. For fault conditions that are just exceeding the limit threshold the response

time for the ALERT pin can vary from 1 to 2 conversion cycles. As mentioned, the variation is due to the timing

on when the fault event occurs relative to the start time of the internal ADC conversion cycle. For fault events

that greatly exceed the limit threshold it is possible for the alert to respond in less than one conversion cycle.

This is because it takes fewer samples for the average to exceed the limit threshold value.

See Table 9

tCT = 140 µs

See Table 11

See Table 12

Figure 39. Alert Response

See Table 10

tCT = 1.1 ms

See Table 11

See Table 12

Figure 40. Alert Response

Table 9. Configuration Register (00h) Settings for Figure 39 (Value = 6006h)

BIT #

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

BIT

NAME

RST

—

—

—

AVG2

AVG1

AVG0

VBUSC

T2

VBUSC

T1

VBUSC

T0

ISHCT2

ISHCT1

ISHCT0

MODE3

MODE2

MODE1

POR

VALUE

0

1

1

0

0

0

0

0

0

0

0

0

0

1

1

0

Table 10. Configuration Register (00h) Settings for Figure 40 (Value = 6126h)

BIT #

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

BIT

NAME

RST

—

—

—

AVG2

AVG1

AVG0

VBUSC

T2

VBUSC

T1

VBUSC

T0

ISHCT2

ISHCT1

ISHCT0

MODE3

MODE2

MODE1

POR

VALUE

0

1

1

0

0

0

0

1

0

0

1

0

0

1

1

0

Table 11. Mask/Enable Register (06h) Settings for Figure 39 and Figure 40 (Value = 2008h)

BIT #

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

BIT

NAME

OCL

UCL

BOL

BUL

POL

CNVR

—

—

—

—

—

AFF

CVRF

OVF

APOL

LEN

POR

VALUE

0

0

1

0

0

0

0

0

0

0

0

0

1

0

0

0