10 k

OPA333

±10-mV

Adjustment Range

100

100

100 mA

1/2 REF200

100 mA

1/2 REF200

V+

V-

R

G

INA826S

REF

V

O

V

IN-

V

IN+

Copyright © 2017, Texas Instruments Incorporated

22

INA826S

SBOS770A – MAY 2017 – REVISED JUNE 2017

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Copyright © 2017, Texas Instruments Incorporated

7.3.3 Offset Trimming

Most applications require no external offset adjustment; however, if necessary, adjustments can be made by

applying a voltage to the REF pin. Figure 66 shows an optional circuit for trimming the output offset voltage. The

voltage applied to the REF pin is summed at the output. The op amp buffer provides low impedance at the REF

pin to preserve good common-mode rejection.

Figure 66. Optional Trimming of Output Offset Voltage

7.3.4 Input Common-Mode Range

The linear input voltage range of the INA826S input circuitry extends from the negative supply voltage to 1 V

below the positive supply, and maintains 84-dB (minimum) common-mode rejection throughout this range. The

common-mode range for most common operating conditions is described in Figure 12 through Figure 18 and

Figure 44 through Figure 46. The INA826S can operate over a wide range of power supplies and VREF

configurations, making a comprehensive guide to common-mode range limits impractical to be provided for all

possible conditions.

The most commonly overlooked overload condition occurs when a circuit exceeds the output swing of A1 and A2,

which are internal circuit nodes that cannot be measured. Calculating the expected voltages at the output of A1

and A2 (see Figure 65) provides a check for the most common overload conditions. The designs of A1 and A2 are

identical and the outputs can swing to within approximately 100 mV of the power-supply rails. For example, when

the A2 output is saturated, A1 may continue to be in linear operation, responding to changes in the noninverting

input voltage. This difference can give the appearance of linear operation but the output voltage is invalid.

A single-supply instrumentation amplifier has special design considerations. To achieve a common-mode range

that extends to single-supply ground, the INA826S employs a current-feedback topology with PNP input

transistors; see Figure 65. The matched PNP transistors Q1 and Q2 shift the input voltages of both inputs up by a

diode drop, and through the feedback network, shift the output of A1 and A2 by approximately 0.8 V. With both

inputs and VREF at single-supply ground (negative power supply), the output of A1 and A2 is well within the linear

range, allowing differential measurements to be made at the GND level. As a result of this input level-shifting, the

voltages at pin 2 and pin 3 are not equal to the respective input pin voltages (pin 1 and pin 4). For most

applications, this inequality is not important because only the gain-setting resistor connects to these pins.