DP83867CSRGZ datasheet(48/129 Pages) TI2

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Table 7-11. Basic Mode Status Register (BMSR), Address 0x0001 (continued)

BIT

BIT NAME

DEFAULT

DESCRIPTION

JABBER DETECT

0, RO/LH

Jabber Detect: This bit only has meaning in 10Mbps mode.

1 = Jabber condition detected.

0 = No Jabber.

This bit is implemented with a latching function, such that the

occurrence of a jabber condition causes the bit to set until the bit

is cleared by a read to this register by the management interface or

by a reset.

EXTENDED CAPABILITY

1, RO/P

Extended Capability:

1 = Extended register capabilities.

0 = Basic register set capabilities only.

7.6.3 PHY Identifier Register #1 (PHYIDR1)

The PHY Identifier Registers #1 and #2 together form a unique identifier for the DP83867. The Identifier consists

of a concatenation of the Organizationally Unique Identifier (OUI), the vendor's model number and the model

revision number. A PHY can return a value of zero in each of the 32 bits of the PHY Identifier if desired. The

PHY Identifier is intended to support network management. Texas Instruments' IEEE assigned OUI is 080028h.

Table 7-12. PHY Identifier Register #1 (PHYIDR1), Address 0x0002

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

OUI_MSB

0010 0000 0000

0000, RO/P

OUI Most Significant Bits: Bits 3 to 18 of the OUI (080028h,) are

stored in bits 15 to 0 of this register. The most significant two bits of

the OUI are ignored (the IEEE standard refers to these as bits 1 and

2).

7.6.4 PHY Identifier Register #2 (PHYIDR2)

Table 7-13. PHY Identifier Register #2 (PHYIDR2), Address 0x0003

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:10

OUI_LSB

1010 00, RO/P

OUI Least Significant Bits:

Bits 19 to 24 of the OUI (080028h) are mapped from bits 15 to 10 of

this register respectively.

9:4

VNDR_MDL

10 0011, RO/P

Vendor Model Number:

The six bits of vendor model number are mapped from bits 9 to 4

(most significant bit to bit 9).

3:0

MDL_REV

0001, RO/P

Model Revision Number:

Four bits of the vendor model revision number are mapped from bits

3 to 0 (most significant bit to bit 3). This field increments for all major

device changes.

DP83867CS, DP83867IS, DP83867E

SNLS504F – OCTOBER 2015 – REVISED JANUARY 2025

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