DP83867CSRGZ datasheet(94/129 Pages) TI2

94 / 129 page

7.6.99 Receive Pattern Byte Mask Register 2 (RXFPBM2)

Table 7-109. Receive Pattern Byte Mask Register 2 (RXFPBM2), Address 0x015D

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

PATTERN_BYTES_

MASK_16_31

0, RW

Masks for bytes 16 to 31 of the pattern. A 1 indicates a mask for the

associated byte.

7.6.100 Receive Pattern Byte Mask Register 3 (RXFPBM3)

Table 7-110. Receive Pattern Byte Mask Register 3 (RXFPBM3), Address 0x015E

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

PATTERN_BYTES_

MASK_32_47

0, RW

Masks for bytes 32 to 47 of the pattern. A 1 indicates a mask for the

associated byte.

7.6.101 Receive Pattern Byte Mask Register 4 (RXFPBM4)

Table 7-111. Receive Pattern Byte Mask Register 4 (RXFPBM4), Address 0x015F

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

PATTERN_BYTES_

MASK_48_63

0, RW

Masks for bytes 48 to 63 of the pattern. A 1 indicates a mask for the

associated byte.

7.6.102 Receive Pattern Control (RXFPATC)

Table 7-112. Receive Status Register (RXFSTS), Address 0x0161

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:6

RESERVED

0, RO

RESERVED: Writes ignored, read as 0.

5:0

PATTERN_START_POINT

0, RW

Number of bytes after SFD where comparison of the RX packet to

the configured pattern begins:

111111 - Start compare in the 64th byte after SFD

000000 - Start compare in the 1st byte after SFD

7.6.103 10M SGMII Configuration (10M_SGMII_CFG)

Table 7-113. 10M SGMII Configuration (10M_SGMII_CFG), Address 0x016F

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:8

RESERVED

0000 0000, RO RESERVED

10M_SGMII_RATE_ADAPT

1, RW

RESERVED - Do not change this bit. The PHY adapts automatically

to 10M speed.

6:0

RESERVED

001 0101, RO

RESERVED

7.6.104 I/O Configuration (IO_MUX_CFG)

Table 7-114. I/O Configuration (IO_MUX_CFG), Address 0x0170

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:13

RESERVED

0, RO

RESERVED

DP83867CS, DP83867IS, DP83867E

SNLS504F – OCTOBER 2015 – REVISED JANUARY 2025

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DP83867CSRGZ Datasheet(PDF) 94 Page - Texas Instruments

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